Search Results - "Chatarasi, Prasanth"

Polyhedral Optimizations of Explicitly Parallel Programs by Chatarasi, Prasanth, Shirako, Jun, Sarkar, Vivek

“…The polyhedral model is a powerful algebraic framework that has enabled significant advances to analysis and transformation of sequential affine (sub)programs,…”
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MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings by Kwon, Hyoukjun, Chatarasi, Prasanth, Sarkar, Vivek, Krishna, Tushar, Pellauer, Michael, Parashar, Angshuman

“…The efficiency of an accelerator depends on three factors-mapping, deep neural network (DNN) layers, and hardware-constructing extremely complicated design…”
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Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication by Moon, Gordon Euhyun, Kwon, Hyoukjun, Jeong, Geonhwa, Chatarasi, Prasanth, Rajamanickam, Sivasankaran, Krishna, Tushar

“…There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements…”
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Extending Polyhedral Model for Analysis and Transformation of OpenMP Programs by Chatarasi, Prasanth, Sarkar, Vivek

“…The polyhedral model is a powerful algebraic framework that has enabled significant advances in analysis and transformation of sequential affine (sub)programs,…”
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FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching by Tong, Jianming, Itagi, Anirudh, Chatarasi, Prasanth, Krishna, Tushar

“…The inference of ML models composed of diverse structures, types, and sizes boils down to the execution of different dataflows (i.e. different tiling,…”
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Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication by Moon, Gordon Euhyun, Kwon, Hyoukjun, Jeong, Geonhwa, Chatarasi, Prasanth, Rajamanickam, Sivasankaran, Krishna, Tushar

“…There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements…”
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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey K., Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Rower, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…Discrete AI inference cards, operating under form-factor and system-defined peak power constraints, must serve diverse inference requests with widely varying…”
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Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators by Jeong, Geonhwa, Kestor, Gokcen, Chatarasi, Prasanth, Parashar, Angshuman, Tsai, Po-An, Rajamanickam, Sivasankaran, Gioiosa, Roberto, Krishna, Tushar

“…To meet the extreme compute demands for deep learning across commercial and scientific applications, dataflow accelerators are becoming increasingly popular…”
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Extending the Polyhedral Compilation Model for Debugging and Optimization of Spmd-Style Explicitly-Parallel Programs by Chatarasi, Prasanth

“…The SPMD (Single Program Multiple Data) parallelism continues to be one of the most popular parallel execution models in use today, as exemplified by OpenMP…”
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14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey, Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Roewer, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…The rapid emergence of AI models, specifically large language models (LLMs) requiring large amounts of compute, drives the need for dedicated AI inference…”
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FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching by Tong, Jianming, Itagi, Anirudh, Chatarasi, Prasanth, Krishna, Tushar

“…The inference of ML models composed of diverse structures, types, and sizes boils down to the execution of different dataflows (i.e. different tiling,…”
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Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine by Chatarasi, Prasanth, Neuendorffer, Stephen, Bayliss, Samuel, Vissers, Kees, Sarkar, Vivek

“…Xilinx's AI Engine is a recent industry example of energy-efficient vector processing that includes novel support for 2D SIMD datapaths and shuffle…”
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Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine by Chatarasi, Prasanth, Neuendorffer, Stephen, Bayliss, Samuel, Vissers, Kees, Sarkar, Vivek

“…Xilinx's AI Engine is a recent industry example of energy-efficient vector processing that includes novel support for 2D SIMD datapaths and shuffle…”
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Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication by Moon, Gordon E, Kwon, Hyoukjun, Jeong, Geonhwa, Chatarasi, Prasanth, Rajamanickam, Sivasankaran, Krishna, Tushar

“…There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements…”
Get full text

Union: A Unified HW-SW Co-Design Ecosystem in MLIR for Evaluating Tensor Operations on Spatial Accelerators by Jeong, Geonhwa, Kestor, Gokcen, Chatarasi, Prasanth, Parashar, Angshuman, Tsai, Po-An, Rajamanickam, Sivasankaran, Gioiosa, Roberto, Krishna, Tushar

“…To meet the extreme compute demands for deep learning across commercial and scientific applications, dataflow accelerators are becoming increasingly popular…”
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Experimental Insights from the Rogues Gallery by Young, Jeffrey S., Riedy, Jason, Conte, Thomas M., Sarkar, Vivek, Chatarasi, Prasanth, Srikanth, Sriseshan

“…The Rogues Gallery is a new deployment for understanding next-generation hardware with a focus on unorthodox and uncommon technologies. This testbed project…”
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Marvel: A Data-centric Compiler for DNN Operators on Spatial Accelerators by Chatarasi, Prasanth, Kwon, Hyoukjun, Raina, Natesh, Malik, Saurabh, Haridas, Vaisakh, Parashar, Angshuman, Pellauer, Michael, Krishna, Tushar, Sarkar, Vivek

“…The efficiency of a spatial DNN accelerator depends heavily on the compiler and its cost model ability to generate optimized mappings for various operators of…”
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Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach Using MAESTRO by Kwon, Hyoukjun, Chatarasi, Prasanth, Pellauer, Michael, Parashar, Angshuman, Sarkar, Vivek, Krishna, Tushar

“…The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse and perform staging are known as dataflow, and they directly impact…”
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