Search Results - "Chao, H.h."

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    Error-specific medial cortical and subcortical activity during the stop signal task: A functional magnetic resonance imaging study by Li, C.-S.R, Yan, P, Chao, H.H.-A, Sinha, R, Paliwal, P, Constable, R.T, Zhang, S, Lee, T.-W

    Published in Neuroscience (09-09-2008)
    “…Abstract The ability to detect errors and adjust behavior accordingly is essential for maneuvering in an uncertain environment. Errors are particularly prone…”
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    Plate-noise analysis of an on-chip generated half-VDD biased-plate PMOS cell in CMOS DRAMs by Lu, N.C.C., Chao, H.H., Hwang, W.

    Published in IEEE journal of solid-state circuits (01-12-1985)
    “…An on-chip generated half-VDD bias for the memory-cell plate is used in CMOS DRAMS to reduce the electric field in the storage insulator such that higher…”
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    Antioxidant activity of Ganoderma lucidum in acute ethanol-induced heart toxicity by Wong, K.L, Chao, H.H, Chan, P, Chang, L.P, Liu, C.F

    Published in Phytotherapy research (01-12-2004)
    “…The hot water extract of the mushroom Ganoderma lucidum was shown to have antioxidative effect against heart toxicity. Investigations into the mechanisms of…”
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    Surface modification and initial adhesion events for intestinal epithelial cells by Hagerman, E.M., Chao, S.H.H., Dunn, J.C.Y., Wu, B.M.

    “…Rapid resealing of the mucosal epithelia is imperative following injuries to the small intestine because the mucosa is responsible for the adsorption of…”
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    Tachykinins preferentially excite certain complex cells in the infragranular layers of feline striate cortex by Albus, K, Chao, H H, Hicks, T P

    Published in Brain research (07-08-1992)
    “…Microiontophoretically administered substance P (SP) affected the visually evoked responses (VER) and the spontaneous firing of 22 (14%) of the 152 neurons…”
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    A 20-ns 128-kbit4 high speed DRAM with 330-Mbit/s data rate by Lu, N.C.C., Chao, H.H., Hwang, W., Henkels, W.H., Rajeevakumar, T.V., Hanafi, H.I., Terman, L.M., Franch, R.L.

    Published in IEEE journal of solid-state circuits (01-10-1988)
    “…The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM…”
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    Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs by Lu, N.C.-C., Chao, H.H.

    Published in IEEE journal of solid-state circuits (01-08-1984)
    “…A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and…”
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    A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology by Chao, H.H., Dennard, R.H., Tsai, M.Y., Wordeman, M.R., Cramer, A.

    Published in IEEE journal of solid-state circuits (01-10-1981)
    “…Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top electrode of a given cell storage…”
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