Search Results - "Chanhee Oh"
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1
Cooperative tumour cell membrane targeted phototherapy
Published in Nature communications (19-06-2017)“…The targeted delivery of therapeutics using antibodies or nanomaterials has improved the precision and safety of cancer therapy. However, the paucity and…”
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Journal Article -
2
Static electromigration analysis for on-chip signal interconnects
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-01-2003)“…With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved…”
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Journal Article -
3
Driver modeling and alignment for worst-case delay noise
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation (01-01-2001)“…In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that…”
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Conference Proceeding -
4
Driver modeling and alignment for worst-case delay noise
Published in IEEE transactions on very large scale integration (VLSI) systems (01-04-2003)“…In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that…”
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5
Inhalation Delivery of Interferon-λ-Loaded Pulmonary Surfactant Nanoparticles Induces Rapid Antiviral Immune Responses in the Lung
Published in ACS applied materials & interfaces (06-03-2024)“…The interferon-λ (IFN-λ)-regulated innate immune responses in the airway expand our understanding toward antiviral strategies against influenza A virus (IAV)…”
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6
Pulmonary Surfactant-Based Paclitaxel-Loaded Nanovesicles for Inhalation Therapy of Lung Adenocarcinoma
Published in ACS applied nano materials (10-03-2023)“…Treatments for lung adenocarcinoma, a type of non-small-cell lung cancer that accounts for about 40% of all lung cancers, are generally administered…”
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7
False-noise analysis for domino circuits
Published in Proceedings Design, Automation and Test in Europe Conference and Exhibition (2004)“…High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use…”
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Conference Proceeding -
8
Efficient logic-level timing analysis using constraint-guided critical path search
Published in IEEE transactions on very large scale integration (VLSI) systems (01-09-1996)“…As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits…”
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9
Post-route gate sizing for crosstalk noise reduction
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003 (02-06-2003)“…Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The…”
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Conference Proceeding -
10
False-noise analysis using logic implications
Published in Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design (2001)“…Cross-coupled noise analysis has become a critical concern in VLSI design. Typically, noise analysis makes the assumption that all aggressing nets can…”
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Conference Proceeding Journal Article -
11
A methodology for chip-level electromigration risk assessment and product qualification
Published in International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720) (2004)“…Even after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the most important reliability…”
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Conference Proceeding -
12
Noise injection and propagation in high performance designs
Published in Proceedings International Symposium on Quality Electronic Design (2002)“…Signal integrity has become a critical issue in the design of high-performance circuits. Noise on a net arises both through propagation of noise from previous…”
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Conference Proceeding -
13
Static electromigration analysis for signal interconnects
Published in Fourth International Symposium on Quality Electronic Design, 2003. Proceedings (2003)“…With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved…”
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Conference Proceeding -
14
Post-route gate sizing for crosstalk noise reduction
Published in Fourth International Symposium on Quality Electronic Design, 2003. Proceedings (2003)“…Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs…”
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Conference Proceeding -
15
Logic-level timing analysis for digital integrated circuits
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Dissertation -
16
Impact of stress-induced backflow on full-chip electromigration risk assessment
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-06-2006)“…This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring…”
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Journal Article -
17
A global driver sizing tool for functional crosstalk noise avoidance
Published in Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design (2001)“…As coupling noise analysis and estimation is reaching a relative maturity with recent efforts, more effort is needed in correcting and/or avoiding failures…”
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Conference Proceeding -
18
Crosstalk noise control in an SoC physical design flow
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-04-2004)“…Signal integrity closure is one of the key challenges in deep submicron physical design. In this paper, we propose a physical design methodology which includes…”
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19
Improved sequential ATPG using functional observation information and new justification methods
Published in Proceedings the European Design and Test Conference. ED&TC 1995 (1995)“…Sequential ATPG (Automatic Test Pattern Generation) is a very desirable CAD tool, but to date, the site and complexity of circuits for which sequential ATPG…”
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Conference Proceeding -
20
Duet: an accurate leakage estimation and optimization tool for dual-V(t) circuits
Published in IEEE transactions on very large scale integration (VLSI) systems (01-04-2002)“…Presents a new approach for the estimation and optimization of standby power dissipation in large MOS digital circuits. We introduce a new approach for…”
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Journal Article