Search Results - "Chang, S.Z."

Modulation of the effective work function of fully-silicided (FUSI) gate stacks by Kittl, J.A., Lauwers, A., Pawlak, M.A., Veloso, A., Yu, H.Y., Chang, S.Z., Hoffmann, T., Pourtois, G., Brus, S., Demeurisse, C., Vrancken, C., Absil, P.P., Biesemans, S.

“…A systematic analysis of the different methods of work function (WF) tuning for gate stacks using fully silicided (FUSI) gate electrodes is presented. We show…”
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The Application of an Ultrathin ALD HfSiON Cap Layer on SiON Dielectrics for Ni-FUSI CMOS Technology Targeting at Low-Power Applications by Chang, S.Z., Yu, H.Y., Veloso, A., Lauwers, A., Delabie, A., Everaert, J-L., Kerner, C., Absil, P., Hoffmann, T., Biesemans, S.

“…In this letter, we report that the application of a thin HfSiON cap layer (2-10 cycles via atomic layer deposition) on SiON host dielectrics in…”
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Electrical Properties of Low- V Metal-Gated n-MOSFETs Using \hbox\hbox/\hbox as Interfacial Layer Between HfLaO High- \kappa Dielectrics and Si Channel by Chang, S.Z., Yu, H.Y., Adelmann, C., Delabie, A., Wang, X.P., Van Elshocht, S., Akheyar, A., Nyns, L., Swerts, J., Aoulaiche, M., Kerner, C., Absil, P., Hoffmann, T.Y., Biesemans, S.

“…In this letter, we report that by employing the La 2 O 3 /SiO x interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta 2 C metal-gated…”
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Demonstration of Low Vt Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a Dy2O3 Cap Layer by Yu, H.Y, Chang, S.Z, Veloso, A, Lauwers, A, Adelmann, C, Onsia, B, Lehnen, P, Kauerauf, T, Brus, S, Yin, K.M, Absil, P, Biesemans, S

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Demonstration of Low V Ni-FUSI N-MOSFETs With SiON Dielectrics by Using a \hbox\hbox Cap Layer by Yu, H.Y., Chang, S.Z., Veloso, A., Lauwers, A., Adelmann, C., Onsia, B., Lehnen, P., Kauerauf, T., Brus, S., Yin, K.M., Absil, P., Biesemans, S.

“…This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide…”
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Electrical Properties of Low-[Formula Omitted] Metal-Gated n-MOSFETs Using [Formula Omitted] as Interfacial Layer Between HfLaO High-[Formula Omitted] Dielectrics and Si Channel by Chang, S.Z, Yu, H.Y, Adelmann, C, Delabie, A, Wang, X.P, Van Elshocht, S, Akheyar, A, Nyns, L, Swerts, J, Aoulaiche, M, Kerner, C, Absil, P, Hoffmann, T.Y, Biesemans, S

“…In this letter, we report that by employing the La sub(2)O sub(3)/SiO sub(x ) interfacial layer between HfLaO (La = 10%) high- and Si channel, the Ta sub(2)C…”
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Demonstration of low Vt Ni-FUSI N-MOSFETs with SiON dielectrics by using a Dy2O3 cap layer by YU, H. Y, CHANG, S. Z, ABSIL, P, BIESEMANS, S, VELOSO, A, LAUWERS, A, ADELMANN, C, ONSIA, B, LEHNEN, P, KAUERAUF, T, BRUS, S, YIN, K. M

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Achieving Low-[Formula Omitted] Ni-FUSI CMOS by Ultra-Thin [Formula Omitted] Capping of Hafnium Silicate Dielectrics by Veloso, A, Yu, H.Y, Chang, S.Z, Adelmann, C, Onsia, B, Brus, S, Demand, M, Lauwers, A, O'Sullivan, B.J, Singanamalla, R, Pourtois, G, Lehnen, P, Van Elshocht, S, De Meyer, K, Jurczak, M, Absil, P.P, Biesemans, S

“…This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the…”
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Achieving Low- V Ni-FUSI CMOS by Ultra-Thin \hbox\hbox Capping of Hafnium Silicate Dielectrics by Veloso, A., Yu, H.Y., Chang, S.Z., Adelmann, C., Onsia, B., Brus, S., Demand, M., Lauwers, A., O'Sullivan, B.J., Singanamalla, R., Pourtois, G., Lehnen, P., Van Elshocht, S., De Meyer, K., Jurczak, M., Absil, P.P., Biesemans, S.

“…This letter reports that the effective work function (eWF) of Ni-Fully Silicided (Ni-FUSI) devices with HfSiON gate dielectrics can be modulated toward the…”
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Demonstration of Metal-Gated Low V n-MOSFETs Using a Poly- \hbox\hbox/\hbox Gate Stack With a Scaled EOT Value by H.Y. Yu, Singanamalla, R., Ragnarsson, L.-A., V.S. Chang, H.-J. Cho, Mitsuhashi, R., Adelmann, C., Van Elshocht, S., Lehnen, P., S.Z. Chang, K.M. Yin, Schram, T., Kubicek, S., De Gendt, S., Absil, P., De Meyer, K., Biesemans, S.

“…In this letter, we report that by using a thin dysprosium oxide (Dy 2 O 3 )cap layer (~1-nm thick) on top of SiON host dielectrics, the threshold voltage (V t…”
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Demonstration of metal-gated low Vt n-MOSFETs using a poly -Si /TaN/Dy2O3/SiON gate stack with a scaled EOT value by YU, H. Y, SINGANAMALLA, R, YIN, K. M, SCHRAM, T, KUBICEK, S, DE GENDT, S, ABSIL, P, DE MEYER, K, BIESEMANS, S, RAGNARSSON, L.-A, CHANG, V. S, CHO, H.-J, MITSUHASHI, R, ADELMANN, C, VAN ELSHOCHT, S, LEHNEN, P, CHANG, S. Z

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Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack by Veloso, A., Yu, H.Y., Lauwers, A., Chang, S.Z., Adelmann, C., Onsia, B., Demand, M., Brus, S., Vrancken, C., Singanamalla, R., Lehnen, P., Kittl, J., Kauerauf, T., Vos, R., O′Sullivan, B.J., Van Elshocht, S., Mitsuhashi, R., Whittemore, G., Yin, K.M., Niwa, M., Hoffmann, T., Absil, P., Jurczak, M., Biesemans, S.

“…This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF)…”
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Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases by Yu, H.Y., Chang, S.Z., Veloso, A., Lauwers, A., Adelmann, C., Onsia, B., Van Elshocht, S., Singanamalla, R., Demand, M., Vos, R., Kauerauf, T., Brus, S., Shi, X., Kubicek, S., Vrancken, C., Mitsuhashi, R., Lehnen, P., Kittl, J., Niwa, M., Yin, K.M., Hoffmann, T., Degendt, S., Jurczak, M., Absil, P., Biesemans, S.

“…This paper reports a novel approach to implement low V t Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host…”
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Low VT metal-gate/high-k nMOSFETs - PBTI dependence and VT Tune-ability on La/Dy-capping layer locations and Laser annealing conditions by Chang, S.Z., Hoffmann, T.Y., Yu, H.Y., Aoulaiche, M., Rohr, E., Adelmann, C., Kaczer, B., Delabie, A., Favia, P., Van Elshocht, S., Kubicek, S., Scharm, T., Witters, T., Ragnarsson, L.A., Wang, X.P., Cho, H.J., Mueller, M., Chiarella, T., Absil, P., Biesemans, S.

“…This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-V T nMOSFETs. We found that…”
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Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack by Veloso, A., Yu, H.Y., Lauwers, A., Chang, S.Z., Adelmann, C., Onsia, B., Demand, M., Brus, S., Vrancken, C., Singanamalla, R., Lehnen, P., Kittl, J., Kauerauf, T., Vos, R., O'Sullivan, B.J., Van Elshocht, S., Mitsuhashi, R., Whittemore, G., Yin, K.M., Niwa, M., Hoffmann, T., Absil, P., Jurczak, M., Biesemans, S.

“…This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (WF)…”
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Integrate LaOx-capping layer into metal gated CMOS devices using a gate-first approach for sub-45nm technology node and the device reliability thereof by HongYu Yu, Chang, S.Z., Kubicek, S., Schram, T., Wang, X.P., Biesemans, S.

“…This paper provides a comprehensive study on the integration of LaO x capping layer for sub-45 nm metal gated CMOS devices with Hf-based high-K dielectrics in…”
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A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications by Wu, C.C., Leung, Y.K., Chang, C.S., Tsai, M.H., Huang, H.T., Lin, D.W., Sheu, Y.M., Hsieh, C.H., Liang, W.J., Han, L.K., Chen, W.M., Chang, S.Z., Wu, S.Y., Lin, S.S., Lin, H.C., Wang, C.H., Wang, P.W., Lee, T.L., Fu, C.Y., Chang, C.W., Chen, S.C., Jang, S.M., Shue, S.L., Lin, H.T., See, Y.C., Mii, Y.J., Diaz, C.H., Lin, B.J., Liang, M.S., Sun, Y.C.

“…A leading edge 90nm bulk CMOS device technology is described in this paper. In this technology, multi Vt and multi gate oxide devices are offered to support…”
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High-k/ metal-gate stack work-function tuning by rare-earth capping layers: Interface dipole or bulk charge? by Yu, H.Y., Chang, S.Z., Aoulaiche, M., Kaczer, B., Absil, P., Adelmann, C., Hoffmann, T., Biesemans, S., Wann, C., Mii, Y.J.

“…The transistor V T tuning mechanism in metal-gate/high-k (MG/HK) gate stack doped with rare-earth elements (Dysprosium or Dy in this work) is studied in…”
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Study of asymmetric broadening of Raman scattering in In/sub x/Ga/sub 1-x/As/InP and In/sub x/Ga/sub 1-x/As/GaAs epilayers by Shen, J.L., Chang, S.Z., Lee, S.C., Chen, Y.F.

“…Raman scattering of In/sub x/Ga/sub 1-x/As epitaxial layers on InP and GaAs substrates have been investigated with a wide range of composition. It is found…”
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Ultra-low leakage 0.16 /spl mu/m CMOS for low-standby power applications by Wu, C.C., Diaz, C.H., Lin, B.L., Chang, S.Z., Wang, C.C., Liaw, J.J., Wang, C.H., Young, K.K., Lee, K.H., Liew, B.K., Sun, J.Y.C.

“…In this work, low leakage 0.16 /spl mu/m CMOS devices (T/sub ox/=32 /spl Aring/) with various off-state leakage currents (I/sub off/) were fabricated and…”
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