Search Results - "Champac, V.H."
-
1
Impact of aging on the SEU immunity of FinFET-based embedded memory systems
Published in Microelectronics and reliability (01-11-2023)Get full text
Journal Article -
2
Detectability conditions for interconnection open defects
Published in Proceedings 18th IEEE VLSI Test Symposium (2000)“…The detectability of interconnection opens by logic and I/sub DDQ/ testing is investigated. Opens in interconnection paths disconnect the driven gate(s) from…”
Get full text
Conference Proceeding
-
3
Testability of floating gate defects in sequential circuits
Published in Proceedings 13th IEEE VLSI Test Symposium (1995)“…The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential…”
Get full text
Conference Proceeding -
4
Resistive opens in a class of CMOS latches: analysis and DFT
Published in Proceedings 19th IEEE VLSI Test Symposium. VTS 2001 (2001)“…The behavior of a class of CMOS latches in the presence of resistive opens is investigated. The detectability of resistive opens by delay testing is analyzed…”
Get full text
Conference Proceeding -
5
Electrical model of the floating gate defect in CMOS ICs: implications on I/sub DDQ/ testing
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-03-1994)“…The behavior of an MOS transistor with an open in the polygate path (floating transistor gate defect) is investigated and its effect on the quiescent power…”
Get full text
Journal Article -
6
I/sub DDQ/ testing of opens in CMOS SRAMs
Published in Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231) (1998)“…The behavior of a CMOS SRAM memory in the presence of open defects is analyzed. It has been found that destructive read-out depends on the level of the…”
Get full text
Conference Proceeding -
7
Analysis and attenuation proposal in ground bounce
Published in 13th Asian Test Symposium (2004)“…The effect of the parasitic values on the ground bounce voltage and on the delay is investigated. Also the effect of ground bounce on the delay in depth paths…”
Get full text
Conference Proceeding -
8
A forced-voltage technique to test data retention faults in CMOS SRAM by I/sub DDQ/ testing
Published in Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg (1997)“…A novel technique to test data retention faults in a static CMOS memory cell is proposed. The proposed technique creates intermediate voltages in the faulty…”
Get full text
Conference Proceeding -
9
The noise immunity of dynamic digital circuits with technology scaling
Published in 2004 IEEE International Symposium on Circuits and Systems (ISCAS) (2004)“…Signal integrity issues are a main concern in high performance circuits due to the higher clock rates and the increased integration complexity. Interconnect…”
Get full text
Conference Proceeding -
10
An improved technique to increase noise-tolerance in dynamic digital circuits
Published in 2004 IEEE International Symposium on Circuits and Systems (ISCAS) (2004)“…Due to the rapid scaling of the transistor and interconnect dimensions the VLSI circuit technology is having an impressive advancement. However, noise issues…”
Get full text
Conference Proceeding -
11
Switching noise due to internal gates: delay implications and modeling
Published in Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) (2000)“…In this paper the ground bounce due to switching of internal CMOS gates is analyzed. The implications of the switching noise on the delay of the switching…”
Get full text
Conference Proceeding -
12
A new technique for noise-tolerant pipelined dynamic digital circuits
Published in 2002 IEEE International Symposium on Circuits and Systems (ISCAS) (2002)“…Noise issues are becoming a main concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem, we…”
Get full text
Conference Proceeding -
13
Dynamic logic styles with improved noise-immunity
Published in Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) (2002)“…Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. Noise effects in deep…”
Get full text
Conference Proceeding -
14
Analysis of the floating gate defect in CMOS
Published in Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (1993)“…The floating gate transistor is modeled using the coupling capacitances in the floating gate and the charge in the transistor gate. The location of the open in…”
Get full text
Conference Proceeding -
15
Testing of resistive opens in CMOS latches and flip-flops
Published in European Test Symposium (ETS'05) (2005)“…Open defects in CMOS memory elements are investigated. The analysis has been carried-out in a class of symmetrical CMOS flip-flop. Main focus is given to high…”
Get full text
Conference Proceeding -
16
A symbolic circuit analysis-oriented algorithm for finding a common tree of the current and voltage graphs
Published in Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) (2000)“…A fundamental problem of symbolic analysis when using the signal flow graph method is to find the common tree of the current and voltage graph (Gi and Gv,…”
Get full text
Conference Proceeding -
17
Design of domino CMOS cells under delay constraint
Published in Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303) (1999)“…Simple expressions to estimate the delay and power consumption of domino gates have been developed. Using these expressions design guidelines are established…”
Get full text
Conference Proceeding -
18
CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS
Published in 1991, Proceedings. International Test Conference (1991)Get full text
Conference Proceeding -
19
A graph-oriented CAD tool for establishing the topological diagnostic conditions of analogue circuits
Published in Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216) (1998)“…The diagnosability of analogue circuits can be assessed in terms of the interconnection pattern of the network, because faulty components introduce…”
Get full text
Conference Proceeding