Search Results - "Cham, K.M."

A study of the trench surface inversion problem in the trench CMOS technology by Cham, K.M., Chiang, S.-Y.

“…This paper presents the results obtained in the study of the trench surface inversion problem for the CMOS technology using trench isolation. Special emphasis…”
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The sloped-wall SWAMI-A defect-free zero bird's-beak local oxidation process for scaled VLSI technology by Chiu, K.Y., Moll, J.L., Cham, K.M., Jung Lin, Lage, C., Angelos, S., Tillman, R.L.

“…A new scheme for a Side WAll Masked Isolation (SWAMI) process is presented which takes all the advantages provided by LOCOS without suffering its difficulties…”
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Accurate delay models for digital BiCMOS by Raje, P.A., Saraswat, K.C., Cham, K.M.

“…A detailed transient analysis of the MOSFET-BJT combination prevalent in digital BiCMOS gates is presented. The analysis accounts for high-level injection…”
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Performance-driven scaling of BiCMOS technology by Raje, P.A., Saraswat, K.C., Cham, K.M.

“…A BiCMOS scaling analysis is carried out to optimize the performance of digital BiCMOS gates while accounting for the conditions that make the direct…”
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Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply by Ritts, R.B., Raje, P.A., Plummer, J.D., Saraswat, K.C., Cham, K.M.

“…The authors discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. MBiCMOS…”
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Device design for the submicrometer p-channel FET with n+polysilicon gate by Cham, K.M., Shang-Yi Chiang

“…CMOS has become one of the most important technologies for VLSI applications. If the conventional n + polysilicon gate approach is to be maintained for VLSI…”
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A new methodology for design of BiCMOS gates and comparison with CMOS by Raje, P.A., Saraswat, K.C., Cham, K.M.

“…A gate comparison methodology is presented to accurately compare the performance of an arbitrary BiCMOS logic gate with a pure CMOS gate. The concept of the…”
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The dependence of hot carrier degradation on AC stress waveforms by Cham, K.M., Fu, H.-s., Nishi, Y.

“…The hot carrier degradation of submicron n-channel FETs is characterized for various gate and drain pulse waveforms. The results are consistent with interface…”
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Optimization of sub-micron p-channel FET structure by Shang-yi Chiang, Cham, K.M., Rung, R.D.

“…The effect of the counter-doping channel implant junction depth (Yj) and the source/drain junction depth (Xj) on the subthreshold characteristics of submicron…”
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An oxide masked p+ source/drain implant for VLSI CMOS by Hui, A.C., Shang-Yi Chiang, Cham, K.M.

“…A process innovation is proposed to help eliminate the p+ implant mask in VLSI CMOS process. After the resist masked n+ source/drain implant, a wet oxidation…”
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Submicrometer thin gate oxide P-channel transistors with P+polysilicon gates for VLSI applications by Cham, K.M., Wenocur, D.W., Lin, J., Lau, C.K., Horng-Sen Fu

“…Submicrometer p-channel transistors have been fabricated using thin (150 Å) gate oxide and p+ polysilicon gates. Favorable device characteristics have been…”
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0.5 Micron BICMOS technology by Momose, H., Cham, K.M., Drowley, C.I., Grinolds, H.R., Fu, H.S.

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Computer-aided design in VLSI device development by Cham, K.M., Oh, S.-Y., Moll, J.L.

“…Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device…”
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Fabrication and characterization of sub-micron thin gate oxide p-channel transistors with p+ polysilicon gates by Wenocur, D.W., Cham, K.M., Lin, J., Lau, C.K., Fu, H.S.

“…Submicron p-channel transistors have been fabricated using thin (150 A) gate oxide and p + polysilicon gates. Quite favorable device characteristics have been…”
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Low power salient integration mode image sensor with a low voltage mixed-signal readout architecture by Chou, Eric Y., Budrys, A. J., Cham, Kit M.

“…CMOS image sensors are very suitable for battery-operated camera systems due to their low power nature. In this research work, a salient integration mode CMOS…”
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Characteristics of submicrometer CMOS transistors in implanted-buried-oxide SOI films by Hashimoto, K., Kamins, T.I., Cham, K.M., Chiang, S.Y.

“…Characteristics of submicrometer MOS transistors on SOI films have been studied. The SOI films were formed by implantation of a buried oxide layer followed by…”
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Characterization and modeling of the trench surface inversion problem for the trench isolated CMOS technology by Cham, K.M., Shang-yi Chiang, Wenocur, D., Rung, R.D.

“…The trench surface inversion problem for the trench isolated CMOS technology was studied with special emphasis on the N-well CMOS technology where the problem…”
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