Search Results - "Chakradhar, S.T."

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques by Lingappan, L., Ravi, S., Raghunathan, A., Jha, N.K., Chakradhar, S.T.

“…In this paper, the authors present compression techniques for effectively reducing the test-data-volume requirements of modern systems-on-a-chip (SOC). Their…”
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Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC by Arora, D., Raghunathan, A., Ravi, S., Sankaradass, M., Jha, N.K., Chakradhar, S.T.

“…The functionality of mobile devices, such as cell phones and personal digital assistants (PDAs), has evolved to include various applications where security is…”
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Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets by Seongmoon Wang, Xiao Liu, Chakradhar, S.T.

“…A novel scan-based delay test approach, referred as the hybrid delay scan, is proposed in this paper. The proposed scan-based delay testing method combines…”
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A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs by Seongmoon Wang, Chakradhar, S.T.

“…In this paper, an automatic test pattern generator (ATPG)-based scan-path test point insertion technique, which can achieve high delay fault coverage for scan…”
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Combinational ATPG theorems for identifying untestable faults in sequential circuits by Agrawal, V.D., Chakradhar, S.T.

“…We give two theorems for identifying untestable faults in sequential circuits. The first, the single-fault theorem, states that if a single fault in a…”
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Cypress: compression and encryption of data and code for embedded multimedia systems by Lekatsas, H., Henkel, J., Chakradhar, S.T., Jakkula, V.

“…Copyright protection of sensitive data plays a significant part in the design of multimedia systems. This article introduces a hardware platform that enables…”
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A methodology for architectural design of multimedia multiprocessor SoCs by Lv, T., Ozer, I.B., Chakradhar, S.T., Jiang Xu, Wolf, W., Henkel, J.

“…Multiprocessor SoCs are increasingly important for multimedia systems. This article presents a methodology for the architectural design of multimedia…”
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Power monitors: a framework for system-level power estimation using heterogeneous power models by Bansal, N., Lahiri, K., Raghunathan, A., Chakradhar, S.T.

“…Power analysis early in the design cycle is critical for the design of low power systems. With the move to system-level specifications and design…”
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Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs by Sethuram, R., Seongmoon Wang, Chakradhar, S.T., Bushnell, M.L.

“…Since structured application specific integrated chip (ASIC) products require very short turn around time, long automatic test pattern generation (ATPG) run…”
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Unknown Blocking Scheme for Low Control Data Volume and High Observability by Seongmoon Wang, Wenlong Wei, Chakradhar, S.T.

“…This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the…”
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Logic simulation and parallel processing by Agrawal, V.D., Chakradhar, S.T.

“…A statistical model is presented of parallel processing based on circuit activity defined as the average number of gates evaluated at a time step. The number…”
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A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding by Seongmoon Wang, Wenlong Wei, Chakradhar, S.T.

“…This paper presents a test data compression scheme that can be used to further improve compressions achieved by LFSR reseeding. The proposed compression…”
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PIDISC: pattern independent design independent seed compression technique by Balakrishnan, K.J., Seongmoon Wang, Chakradhar, S.T.

“…A novel scheme for compressing the seeds of a linear feedback shifter register (LFSR) is presented. Instead of storing the seeds of the LFSR in the tester, the…”
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A low cost test data compression technique for high n-detection fault coverage by Seongmoon Wang, Zhanglei Wang, Wenlong Wei, Chakradhar, S.T.

“…This paper presents a test data compression scheme that combines weighted random pattern testing and LFSR reseeding. Test patterns generated by the proposed…”
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Efficient Unknown Blocking Using LFSR Reseeding by Seongmoon Wang, Balakrishnan, B.J., Chakradhar, S.T.

“…This paper presents an efficient method to block unknown values from entering temporal compactors. The control signals for the blocking logic are generated by…”
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XWRC: externally-loaded weighted random pattern testing for input test data compression by Seongmoon Wang, Balakrishnan, K.J., Chakradhar, S.T.

“…This paper presents an input test data compression scheme that combines the advantages of weighted pseudorandom testing techniques and LFSR reseeding. The…”
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Distance restricted scan chain reordering to enhance delay fault coverage by Wei Li, Seongmoon Wang, Chakradhar, S.T., Reddy, S.M.

“…This paper presents a new technique to improve the delay fault coverage by re-ordering flip-flops in a scan chain. Unlike prior techniques where scan…”
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Zero Cost Test Point Insertion Technique for Structured ASICs by Sethuram, R., Seongmoon Wang, Chakradhar, S.T., Bushnell, M.L.

“…We show different ways in which unused multiplexers (MUXes) and scan flip-flops (flops) in a structured application specific integrated chip (SA) design can be…”
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Peripheral partitioning and tree decomposition for partial scan by Balakrishnan, A., Chakradhar, S.T.

“…We propose a new partial scan technique that incurs significantly less area overhead than the pipeline technique (all feedback cycles including self-loops are…”
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Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC by Arora, Divya, Raghunathan, Anand, Ravi, Srivaths, Sankaradass, Murugan, Jha, Niraj K., Chakradhar, Srimat T.

“…We present a systematic methodology for exploring the security processing software architecture for a commercial heterogeneous multiprocessor system-on-chip…”
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