Search Results - "Cayrefourcq, I."

Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility by Xiong, W., Cleavelin, C.R., Kohli, P., Huffman, C., Schulz, T., Schruefer, K., Gebara, G., Mathews, K., Patruno, P., Le Vaillant, Y.-M., Cayrefourcq, I., Kennard, M., Mazure, C., Shin, K., Liu, T.-J.K.

“…In this letter, it is shown that for fin widths down to < 20 nm, strain can be retained in patterned strained-silicon-on-insulator (sSOI) films and is…”
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Investigation of strain states and thermal stability of strained-Si-on-Insulator (sSOI) structures by Hoshi, Y., Fukumoto, A., Sawano, K., Cayrefourcq, I., Yoshimi, M., Shiraki, Y.

“…Thermal stability of strained SOI fabricated by Smart Cut technique was found to be high enough for the current Si process, particularly with SiO 2 protection…”
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Stress Hybridization for Multigate Devices Fabricated on Supercritical Strained-SOI (SC-SSOI) by Collaert, N., Rooyackers, R., De Keersgieter, A., Leys, F.E., Cayrefourcq, I., Ghyselen, B., Loo, R., Jurczak, M.

“…In this letter, we investigate the impact of a hybridized strain technology on the performance of FinFET-based multigate field-effect transistors (MUGFETs)…”
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Angle-resolved XPS study of thin oxides after wet cleaning on Si0.8 Ge0.2 substrates by Martinez, E., Abbadie, A., Renault, O., Cayrefourcq, I., Quiais-Marthon, S.

“…One challenge in the downscaling of complementary metal‐oxide semiconductors (CMOSs) is surface cleaning without the use of strong chemical and mechanical…”
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Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements by Gallon, C., Fenouillet-Beranger, C., Bresson, N., Cristoloveanu, S., Allibert, F., Bord, S., Aulnette, C., Delille, D., Latu-Romain, E., Hartmann, J.M., Ernst, T., Andrieu, F., Campidelli, Y., Ghyselen, B., Cayrefourcq, I., Fournel, F., Kernevez, N., Skotnicki, T.

“…Pseudo-MOS (Ψ -MOSFET) measurements are a simple and rapid technique for an accurate evaluation of SOI wafer intrinsic electrical properties, prior to any CMOS…”
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New layer transfers obtained by the SmartCut process by MORICEAU, H, FOURNEL, F, SOUBIE, A, BIASSE, B, SOUSBIE, N, SARTORI, S, MICHAUD, J. F, LETERTRE, F, RAYSSAC, O, CAYREFOURCQ, I, RICHTARCH, C, DAVAL, N, ASPAR, B, AULNETTE, C, AKATSU, T, OSTERNAUD, B, GHYSELEN, B, MAZURE, C, BATAILLOU, B, BEAUMONT, A, MORALES, C, CARTIER, A. M, POCAS, S, LAGAHE, C, JALAGUIER, E

“…The SmartCut process was first developed to obtain Si-on-insulator (SOI) materials. Now an industrial process, the main Unibond SOI-structure trends are…”
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Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI) by Mazure, C., Cayrefourcq, I., Mogab, J., Venkatesan, S., White, B.E., Nguyen, B.-Y., White, T., Burnett, D., La, L.-B., Backer, S., Prabhu, L., Dhandapani, V., Goolsby, B., Wang, X.-D., Goedeke, D., Filipiak, S., Spencer, G., Murphy, S., Shi, Z.-H., Gu, B., Grudowski, P., Desjardin, H., Canonico, M., Conner, J., Adams, V., Vartanian, V., Zhang, D., Thean, A.V.-Y.

“…This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride…”
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Straightforward Integration Flow of a Silicon-Containing Block Copolymer for Line–Space Patterning by Legrain, Antoine, Fleury, Guillaume, Mumtaz, Muhammad, Navarro, Christophe, Arias-Zapata, Javier, Chevalier, Xavier, Cayrefourcq, Ian, Zelsmann, Marc

“…A promising alternative for the next-generation lithography is based on the directed self-assembly of block copolymers (BCPs) used as a bottom-up tool for the…”
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Hydrogen implantation-induced defects in bulk Si studied by Raman spectrometry by Villeneuve, C., Paillard, V., Bourdelle, K.K., Cayrefourcq, I., Boussagol, A., Kennard, M.

“…Ion implantation is a subject of interest because it is widely used in the semiconductor industry, to modify the carrier density in a transistor channel region…”
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Performance Enhancement of MUGFET Devices Using Super Critical Strained-SOI (SC-SSOI) and CESL by Collaert, N., Rooyackers, R., Clemente, F., Zimmerman, P., Cayrefourcq, I., Ghyselen, B., San, K., Eyckens, B., Jurczak, M., Biesemans, S.

“…This paper describes the performance of nMOS and pMOS tall triple gate (MUGFET) devices with fin widths down to 20 nm fabricated for the first time on super…”
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Angle‐resolved XPS study of thin oxides after wet cleaning on Si 0.8 Ge 0.2 substrates by Martinez, E., Abbadie, A., Renault, O., Cayrefourcq, I., Quiais‐Marthon, S.

“…Abstract One challenge in the downscaling of complementary metal‐oxide semiconductors (CMOSs) is surface cleaning without the use of strong chemical and…”
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Ultra-Thin Fully Depleted SOI Devices with Thin BOX, Ground Plane and Strained Liner Booster by Gallon, C., Fenouillet-Beranger, C., Vandooren, A., Boeuf, F., Monfray, S., Payet, F., Orain, S., Fiori, V., Salvetti, F., Loubet, N., Charbuillet, C., Toffoli, A., Allain, F., Romanjek, K., Cayrefourcq, I., Ghyselen, B., Mazure, C., Delille, D., Judong, F., Perrot, C., Hopstaken, M., Scheblin, P., Rivallin, P., Brevard, L., Faynot, O., Cristoloveanu, S., Skotnicki, T.

“…The fully depleted (FD) SOI MOSFET is generally considered as one of the best candidates for next CMOS technology nodes. However, new technological boosters…”
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Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements by Gallon, C., Fenouillet-Beranger, C., Bresson, N., Cristoloveanu, Sorin, Allibert, Michel, Bord, S., Aulnette, C., Delille, Dominique, Latu-Romain, Eddy, Hartmann, Jean-Michel, Ernst, T., Andrieu, F., Campidelli, Y., Ghyselen, B., Cayrefourcq, I., Fournel, F., Kernevez, N., Skotnicki, T.

“…Pseudo-MOS (Ψ -MOSFET) measurements are a simple and rapid technique for an accurate evaluation of SOI wafer intrinsic electrical properties, prior to any CMOS…”
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Status of device mobility enhancement through strained silicon engineering by Mazure, C., Cayrefourcq, I.

“…Strained silicon engineering has become a key innovation to enhance device on-current. It has allowed the IC industry to keep on the scaling path and assure a…”
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25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack by Deleonibus, S., Mazure, C., Gaud, P., Grampeix, H., Colonna, J.P., Previtali, B., Dansas, H., Lafond, D., Jahan, C., Fenouillet-Beranger, C., Ernst, T., Denorme, S., Vandooren, A., Cluzel, J., Barbe, J.C., Allain, F., Brevard, L., Cayrefoureq, I., Ghyselen, B., Casse, M., Rouchouze, E., Buj, C., Tosti, L., Faynot, O., Rochette, F., Dupre, C., Andrieu, F.

“…We investigate for the first time the experimental performance of strained silicon directly on insulator (sSOI) for short and narrow FDSOI NMOS transistors…”
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Performance of super-critical strained-Si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology by Thean, A.V.Y., White, T., Sadaka, M., McCormick, L., Ramon, M., Mora, R., Beckage, P., Canonico, M., Wang, X.-D., Zollner, S., Murphy, S., Van Der Pas, V., Zavala, M., Noble, R., Zia, O., Kang, L.-G., Kolagunta, V., Cave, N., Cheek, J., Mendicino, M., Nguyen, B.-Y., Orlowski, M., Venkatesan, S., Mogab, J., Chang, C.H., Chiu, Y.H., Tuan, H.C., See, Y.C., Liang, M.S., Sun, Y.C., Cayrefourcq, I., Metral, F., Kennard, M., Mazure, C.

“…This paper describes the performance of multiple-V/sub T/, Triple-gate oxide SC-SSOI CMOS realized with Freescale's high-performance silicon-on-insulator…”
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FinFET Performance Enhancement with Tensile Metal Gates and Strained Silicon on Insulator (sSOI) Substrate by Xiong, Weize, Shin, Kyoungsub, Cleavelin, C. Rinn, Schulz, Thomas, Schruefer, Klaus, Cayrefourcq, I., Kennard, M., Mazure, C., Patruno, Paul, Liu, Tsu-jae King

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Impact of Mobility Boosters (XsSOI, CESL, TiN gate) on the Performance of or oriented FDSOI cMOSFETs for the 32nm Node by Andrieu, F., Aussenac, F., Feruglio, S., Eymery, J., Akatsu, T., Maury, P., Brevard, L., Tosti, L., Dansas, H., Rouchouze, E., Hartmann, J.-M., Faynot, O., Vandroux, L., Casse, M., Boeuf, F., Fenouillet-Beranger, C., Brunier, F., Cayrefourcq, I., Mazure, C., Ghibaudo, G., Deleonibus, S., Rochette, F., Barbe, J.-C., Buj, C., Bogumilowicz, Y., Allain, F., Delaye, V., Lafond, D.

“…For the first time, we integrated 1.9GPa eXtra-strained silicon on insulator (XsSOI) substrates in FDSOI n and pMOSFETs with gate length (L G ) and width (W)…”
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Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack by Barral, V., Poiroux, T., Andrieu, F., Buj-Dufournet, C., Faynot, O., Ernst, T., Brevard, L., Fenouillet-Beranger, C., Lafond, D., Hartmann, J.M., Vidal, V., Allain, F., Daval, N., Cayrefourcq, I., Tosti, L., Munteanu, D., Autran, J.L., Deleonibus, S.

“…Scalability of both unstrained and strained FDSOI CMOSFETs is explored for the first time down to 2.5 nm film thickness and 18 nm gate length with HfO 2 /TiN…”
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Tapped delay line dynamic gain flattening filter by Vallon, S., Cayrefourcq, I., Chevallier, P., Landru, N., Alibert, G., Laborde, P., Little, J., Ranalli, A., Boos, N.

“…Experimental results of an 8 tap dynamic gain flattening filter (DGFF) are presented. This device consists in a planar silica on silicon lightwave optical…”
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