Search Results - "Cave, Nigel"

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  1. 1
    Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction

    Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction by Greene, Andrew, Zhou, Huimei, Xie, Ruilong, Park, Chanro, Economikos, Laertis, Chan, Victor, Akarvardar, Kerem, Bao, Ruqiang, Seshadri, Indira, Conti, Richard, Wang, Miaomiao, Sankarapandian, Muthumanickam, Demarest, James, Li, Juntao, Jiang, Liying, Zhao, Kai, Robison, Robert, Ando, Takashi, Cave, Nigel, Knorr, Andreas, Gupta, Dinesh, Kanakasabapathy, Sivananda, Guo, Dechao, Haran, Bala, Basker, Veeraraghavan, Bu, Huiming

    Published in 2019 Symposium on VLSI Technology (01-06-2019)
    “…In this paper, we present for the first time a "Gate-Cut-Last" integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut…”
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  2. 2
    Novel Synthetic Routes to Carbon-Nitrogen Thin Films

    Novel Synthetic Routes to Carbon-Nitrogen Thin Films by Kouvetakis, J, Todd, Michael, Wilkens, Barry, Bandari, Anil, Cave, Nigel

    Published in Chemistry of materials (01-06-1994)
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  3. 3
    A Novel Technique for Probing the Vertical Component of FinFET Source Resistance

    A Novel Technique for Probing the Vertical Component of FinFET Source Resistance by Wang, Peng, Yu, Mickey, Cave, Nigel, Nowak, Edward J.

    Published in IEEE transactions on electron devices (01-12-2021)
    “…We propose and demonstrate, with hardware, the first experimental technique to measure a vertical component of FinFET source resistance. Forward bias is…”
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  4. 4
    Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm

    Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm by Xie, Ruilong, Park, Chanro, Conti, Richard, Robison, Robert, Zhou, Huimei, Saraf, Iqbal, Carr, Adra, Fan, Susan Su Chen, Ryan, Kevin, Belyansky, Michael, Pancharatnam, Shanti, Young, Albert, Wang, Junli, Greene, Andrew, Cheng, Kangguo, Li, Juntao, Conte, Richard, Tang, Hao, Choi, Kisik, Amanapu, Hari, Peethala, Brown, Muthinti, Raja, Raymond, Mark, Prindle, Christopher, Liang, Yong, Tsai, Stan, Kamineni, Vimal, Labonte, Andre, Cave, Nigel, Gupta, Dinesh, Basker, Veeraraghavan, Loubet, Nicolas, Guo, Dechao, Haran, Bala, Knorr, Andreas, Bu, Huiming

    Published in 2019 Symposium on VLSI Technology (01-06-2019)
    “…We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling…”
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  5. 5
    Blanket SMT With In Situ N2 Plasma Treatment on the (100) Wafer for the Low-Cost Low-Power Technology Application

    Blanket SMT With In Situ N2 Plasma Treatment on the (100) Wafer for the Low-Cost Low-Power Technology Application by JUN YUAN, CHAN, Victor, BELYANSKY, Michael P, ELLER, Manfred, YONG MENG LEE, CAVE, Nigel, HUILING SHANG, YING LI, DIVAKARUNI, Rama, ROVEDO, Nivo, SARDESAI, Viraj, KANIKE, Narasimhulu, VARADARAJAN, Vidya, YU, Mickey, JONG HO YANG, JEONG, Y. K, SUNG KWON, O

    Published in IEEE electron device letters (01-09-2009)
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  6. 6
    1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

    1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations by Grudowski, P., Adams, V., Bo, X.-Z., Loiko, K., Filipiak, S., Hackenberg, J., Jahanbani, M., Azrak, M., Goktepeli, S., Shroff, M., Liang, W.-J., Lian, S., Kolagunta, V., Cave, N., Wu, C.-H., Foisy, M., Tuan, H., Cheek, J.

    “…We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry…”
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  7. 7
    The onset of secondary phase precipitation during synthesis of heteroepitaxial Si1− x − y Ge x C y on Si(100)

    The onset of secondary phase precipitation during synthesis of heteroepitaxial Si1− x − y Ge x C y on Si(100) by Herbots, Nicole, Ye, Peihua, Jacobsson, Harald, Xiang, Joan, Hearne, Sean, Cave, Nigel

    Published in Applied physics letters (05-02-1996)
    “…An upper temperature limit of 450 °C has been established for growth of heteroepitaxial Si1−x−yGexCy solid solutions with substitutional C on Si(100) by…”
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  8. 8
    Directing the Tunneller's War

    Directing the Tunneller's War by Cave, Nigel

    Published in Military history (Herndon, Va.) (01-07-2021)
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  9. 9
    Vdd impact on propagation pulse width variation in PD SOI circuits

    Vdd impact on propagation pulse width variation in PD SOI circuits by Min, B.W., Workman, G., Duckhyun Chang, Zia, O., Yanyao Yu, Widenhofer, R., Simon, B., Cave, N., Sanchez, H., Veeraraghavan, S., Mendicino, M., Yeargain, B.

    “…Pulse width variation through open-ended chains in partially depleted SOI is investigated. Vdd impact on the pulse variation (either compression or stretching)…”
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  10. 10
    The adsorption and adhesion of long-chained organosilicon primers

    The adsorption and adhesion of long-chained organosilicon primers by Cave, Nigel Graeme

    Published 01-01-1990
    “…The present research has evaluated the potential of long-chained trichlorosilanes as adhesion promoters. The commercial adhesion promoter,…”
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    Dissertation
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  11. 11
    A 45 nm gate length high performance SOI transistor for 100nm CMOS technology applications

    A 45 nm gate length high performance SOI transistor for 100nm CMOS technology applications by CELIK, Muhsin, KRISHNAN, Srinath, PING YEH, BURBACH, Gert, TAYLOR, Bill, YONGJOO JEON, QI, Wen-Jie, RUIGANG LI, CONNER, Jim, YEAP, Geoffrey, WOO, Michael, MENDICINO, Mike, FUSELIER, Mark, KARLSSON, Olov, WRISTERS, Dirk, WEI, Andy, WU, David, EN, Bill, CAVE, Nigel, ABRAMOWITZ, Peter, BYOUNG MIN, PELELLA, Mario

    Published 2002
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