Search Results - "Casseau, E"

Constrained algorithmic IP design for system-on-chip by Coussy, P., Casseau, E., Bomel, P., Baganne, A., Martin, E.

“…In the system on chip design context, RTL design of complex digital signal processing coprocessors can be improved by using algorithmic description as input…”
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Scheduling, binding and routing system for a run-time reconfigurable operator based multimedia architecture by Raffin, E, Wolinski, C, Charot, F, Kuchcinski, K, Guyetant, S, Chevobbe, S, Casseau, E

“…This paper presents a system for application scheduling, binding and routing for a run-time reconfigurable operator based multimedia architecture (ROMA). We…”
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SoC design using behavioral level virtual components by Casseau, E.

“…While SoC design and virtual component (VC) reuse are on their way to becoming unavoidable practices, the increasing complexity of applications and of VCs…”
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Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis by Le Gal, Bertrand, Casseau, Emmanuel, Huet, Sylvain

“…Multimedia applications such as video and image processing are often characterized by a huge number of data accesses. In many digital signal processing…”
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Efficient software synthesis of dynamic dataflow programs by Yviquel, H., Sanchez, A., Jaaskelainen, P., Takala, J., Raulet, M., Casseau, E.

“…This paper introduces advanced software synthesis techniques that enhance the implementation of dynamic dataflow programs. These techniques have been…”
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SoC design case study using SystemC specifications by Abbes, F., Casseau, E., Abid, M.

“…Modern systems become more and more complex and tendency turn to the integration on one single chip: System on Chip (SoC). A major constraint consists of…”
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Architecture of a high-rate VLSI Viterbi decoder by Casseau, E., Luthi, E.

“…The Viterbi algorithm is widely applied to problems of the state estimation of a finite-state discrete-time Markov process, such as convolutional and trellis…”
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IP integration methodology for SoC design by Abbes, F., Casseau, E., Abid, M., Coussy, P., Legoff, J.B.

“…Integrating intellectual property (IP) components into system-on-chip (SoC) designs requires the use of a generic parameterizable hardware/software interface…”
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High-level synthesis assisted rapid prototyping for digital signal processing by Le Gal, B., Casseau, E., Bomel, P., Jego, C., Le Heno, N., Martin, E.

“…The increasing needs of higher data rates associated with mobility constraints motivate the development of digital satellite news gathering (DSNG) and digital…”
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Exploiting reconfigurable SWP operators for multimedia applications by Menard, D., Nguyen, H. N., Charot, F., Guyetant, S., Guillot, J., Raffin, E., Casseau, E.

“…Implementing image processing applications in embedded systems is a difficult challenge due to the drastic constraints in terms of cost, energy consumption and…”
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High-level synthesis and behavioral VHDL writing style towards a methodology for behavioral IP reuse by Savaton, G., Casseau, E., Martin, E.

“…The recent emergence of commercial high-level synthesis tools raises the question of specifying IPs at the algorithmic, or behavioral, level. While flexibility…”
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Real time application architectural synthesis dedicated to sub-micron technologies by Jego, C., Casseau, E., Martin, E.

“…Architectural synthesis tools map algorithms to architectures under real time constraints and quickly provide estimations of area and performance. However,…”
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High rate soft output Viterbi decoder by Luthi, E., Casseau, E.

“…This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s, 8 states, R=1/2), using the "radix" trellis method to speed up the…”
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Hardware virtual components compliant with communication system standards by Abdelli, N., Bomel, P., Casseau, E., Fouilliart, A.-M., Jego, C., Kajfasz, P., Le Gal, B., Le Heno, N.

“…In this paper, we focus on the design of a communication system based on reusing IP cores. Traditional methods for designing hardware cores for this kind of…”
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Constrained algorithmic IP design for system-on-chip: Systems-on-chip: Design and test by COUSSY, P, CASSEAU, E, BOMEL, P, BAGANNE, A, MARTIN, E

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High-level synthesis for the design of FPGA-based signal processing systems by Casseau, E., Le Gal, B.

“…High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to…”
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Efficient maximal convex custom instruction enumeration for extensible processors by Chenglong Xiao, Casseau, E.

“…In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with…”
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Efficient multicore scheduling of dataflow process networks by Yviquel, H., Casseau, E., Wipliez, M., Raulet, M.

“…Although multi-core processors are now available everywhere, few applications are able to truly exploit their multiprocessing capabilities. Dataflow…”
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Efficient custom instruction enumeration for extensible processors by Chenglong Xiao, Casseau, E.

“…In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with…”
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Stochastic modeling for floating-point to fixed-point conversion by Banciu, A., Casseau, E., Menard, D., Michel, T.

“…The floating-point to fixed-point transformation process is error prone and time consuming as the distortion introduced by the limited data size is difficult…”
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