Search Results - "Cassé, Mikael"

Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K by Cassé, Mikaël, Cardoso Paz, Bruna, Ghibaudo, Gérard, Poiroux, Thierry, Vincent, Emmanuel, Galy, Philippe, Juge, André, Gaillard, Fred, de Franceschi, Silvano, Meunier, Tristan, Vinet, Maud

“…We report the observation at low temperature of a hump in the linear transfer characteristic of a thin film fully depleted silicon-on-insulator transistor when…”
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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures by de Souza, Michelly, Cerdeira, Antonio, Estrada, Magali, Cassé, Mikaël, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo A.

“…•The gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors at high temperatures of operation is experimentally assessed for the first…”
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Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications by Cardoso Paz, Bruna, Casse, Mikael, Theodorou, Christoforos, Ghibaudo, Gerard, Kammler, Thorsten, Pirro, Luca, Vinet, Maud, de Franceschi, Silvano, Meunier, Tristan, Gaillard, Fred

“…This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental…”
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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K by Mariniello, Genaro, Barraud, Sylvain, Vinet, Maud, Cassé, Mikael, Faynot, Olivier, Calcade, Jaime, Antonio Pavanello, Marcelo

“…•The impact higher temperatures are noticed by the increase of Ioff and the decrease of Ion, on stacked vertically nanowire devices.•The reduction of μr…”
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Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures by de Souza, Michelly, Cerdeira, Antonio, Estrada, Magali, Cassé, Mikaël, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo A.

“…•The gate-induced drain leakage (GIDL) in stacked nanowire transistors for temperatures of operation between 300 K and 580 K is experimentally assessed for…”
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Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors by da Silva, Lucas Mota Barbosa, Pavanello, Marcelo Antonio, Cassé, Mikaël, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, de Souza, Michelly

“…•This work presents experimental results of the series resistance variability in junctionless and inversion-mode nanowire transistors.•Due to series…”
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Front and back channels coupling and transport on 28 nm FD-SOI MOSFETs down to liquid-He temperature by Paz, Bruna Cardoso, Cassé, Mikaël, Haendler, Sebastien, Juge, Andre, Vincent, Emmanuel, Galy, Philippe, Arnaud, Franck, Ghibaudo, Gérard, Vinet, Maud, de Franceschi, Silvano, Meunier, Tristan, Gaillard, Fred

“…•Back bias offers a unique way to optimize devices operating at low temperature.•Forward back biasing allows reducing the power consumption.•Electrostatics can…”
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Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures by Bergamaschi, Flavio Enrico, Frutuoso, Tadeu Mota, Paz, Bruna Cardoso, Billiot, Gerard, Jansen, Aloysius G. M., Galy, Phillipe, Vincent, Emmanuel, Gaillard, Fred, Duriez, Blandine, Casse, Mikael

“…Thermal effects are a major concern for efficient cryoCMOS circuit design. This work presents an experimental analysis of self-heating (SH) effects and thermal…”
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Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology by Berlingard, Quentin, Lugo-Alvarez, Jose, Bawedin, Maryline, Contamin, Lauriane, Galy, Philippe, De Franceschi, Silvano, Meunier, Tristan, Vinet, Maud, Gaillard, Fred, Cassé, Mikaël

“…This paper aims to benchmark the threshold voltage extraction at cryogenic temperature. It presents two DC and for the first time one RF methods to extract the…”
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Electrical characterization of stacked SOI nanowires at low temperatures by Rodrigues, Jaime C., Mariniello, Genaro, Cassé, Mikael, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo A.

“…[Display omitted] This work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature…”
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Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures by Prates, Rhaycen R., Barraud, Sylvain, Casse, Mikael, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo A.

“…This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar…”
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High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs by de Souza, Michelly, Cerdeira, Antonio, Estrada, Magali, Barraud, Sylvain, Casse, Mikael, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo Antonio

“…In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects…”
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Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs by Paz, Bruna Cardoso, Cassé, Mikaël, Barraud, Sylvain, Reimbold, Gilles, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo Antonio

“…This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown…”
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FDSOI MOSFET Subthreshold Slope Model Accuracy Improvement Introducing Low-Field Quantum Mechanical Correction by Bedecarrats, Thomas, Triozon, Francois, Martinie, Sebastien, Casse, Mikael, Rozeau, Olivier

“…This paper presents an analytical expression for the FDSOI MOSFETs subthreshold slope model accounting for low electric field quantum mechanical effect. The…”
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Statistical and Electrical Modeling of FDSOI Four-Gate Qubit MOS Devices at Room Temperature by Catapano, Edoardo, Ghibaudo, Gerard, Casse, Mikael, Frutuoso, Tadeu Mota, Paz, Bruna Cardoso, Bedecarrats, Thomas, Apra, Agostino, Gaillard, Fred, De Franceschi, Silvano, Meunier, Tristan, Vinet, Maud

“…This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear…”
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Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs by Paz, Bruna Cardoso, Cassé, Mikaël, Barraud, Sylvain, Reimbold, Gilles, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo Antonio

“…•A methodology is proposed to separate mobility of each level of stacked NW structure.•Lower low filed mobility is obtained for top GAA level comparing to Ω…”
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Electrical characterization of vertically stacked p-FET SOI nanowires by Cardoso Paz, Bruna, Cassé, Mikaël, Barraud, Sylvain, Reimbold, Gilles, Vinet, Maud, Faynot, Olivier, Antonio Pavanello, Marcelo

“…•New approaches and adapted methodologies to extract EOT and real fin width of NWs.•Validation of the extracted parameters by tridimensional numerical…”
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Ultra-Low-Voltage UTBB-SOI-Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications by Nibhanupudi, S. S. Teja, Sundara Raman, Siddhartha Raman, Casse, Mikael, Hutin, Louis, Kulkarni, Jaydeep P.

“…Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can…”
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Carrier transport in HfO2/metal gate MOSFETs : Physical insight into critical parameters by CASSE, Mikaël, THEVENOD, Laurent, BILLON, Thierry, MOUIS, Mireille, BOULANGER, Fabien, GUILLAUMOT, Bernard, TOSTI, Lucie, MARTIN, Francois, MITARD, Jérome, WEBER, Olivier, ANDRIEU, Francois, ERNST, Thomas, REIMBOLD, Gilles

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Mobility comparison between front and back channels in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors by the front-gate split capacitance-voltage method by Ohata, Akiko, Cristoloveanu, Sorin, Cassé, Mikael

“…The mobilities of the front and back channels in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors with a thin (2nm) gate oxide…”
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