Search Results - "Cartier, Eduard"

Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode by Dubourdieu, Catherine, Bruley, John, Arruda, Thomas M., Posadas, Agham, Jordan-Sweet, Jean, Frank, Martin M., Cartier, Eduard, Frank, David J., Kalinin, Sergei V., Demkov, Alexander A., Narayanan, Vijay

“…Epitaxial growth of SrTiO 3 on silicon by molecular beam epitaxy has opened up the route to the integration of functional complex oxides on a silicon platform…”
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Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- k -Metal-Gate CMOS Technologies by Khan, Faraz, Cartier, Eduard, Woo, Jason C. S., Iyer, Subramanian S.

“…The availability of on-chip non-volatile memory for advanced high-k-metal-gate CMOS technology nodes has been limited due to integration and scaling challenges…”
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A maximum extreme-value distribution model for switching conductance of oxide-RRAM in memory applications by Wu, Ernest, Ando, Takashi, Kim, Youngseok, Muralidhar, Ramachandran, Cartier, Eduard, Jamison, Paul, Wang, Miaomiao, Narayanan, Vijay

“…In this work, we report an extensive experimental investigation of the important statistical properties of resistive random access memory (RRAM) switching…”
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Identification of structural phases in ferroelectric hafnium zirconium oxide by density-functional-theory-assisted EXAFS analysis by Sahiner, Mehmet Alper, Vander Valk, Rory J., Steier, Joshua, Savastano, Jared, Kelty, Stephen, Ravel, Bruce, Woicik, Joseph C., Ogawa, Yohei, Schmidt, Kristin, Cartier, Eduard A., Jordan-Sweet, Jean L., Lavoie, Christian, Frank, Martin M.

“…Crystalline phase identification for hafnium-based ferroelectrics by diffraction techniques has been elusive. We use density-functional-theory (DFT)-assisted…”
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Pulse-Train Method to Measure Transient Response of Field-Effect Transistors by Jenkins, Keith A., Cartier, Eduard A., Yau, Jeng-Bang

“…A simple method to measure the short time-domain output current of field-effect transistors (FETs) is demonstrated. By applying short gate pulses and measuring…”
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Origins of Effective Work Function Roll-Off Behavior for High-κ Last Replacement Metal Gate Stacks by Ando, Takashi, Cartier, Eduard A., Bruley, John, Choi, Kisik, Narayanan, Vijay

“…Origins of effective work function (EWF) roll-off behavior accompanied by equivalent oxide thickness (EOT) scaling for high- κ last replacement metal gate…”
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Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- k Stacks by Kerber, A., Krishnan, S.A., Cartier, E.A.

“…A novel voltage-ramp-stress (VRS) methodology is introduced for bias temperature instability testing of metal-gate/high- k (MG/HK) CMOS devices. Results from…”
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Evolution of interfacial Fermi level in In0.53Ga0.47As/high-κ/TiN gate stacks by Carr, Adra, Rozen, John, Frank, Martin M., Ando, Takashi, Cartier, Eduard A., Kerber, Pranita, Narayanan, Vijay, Haight, Richard

“…The net charge state was probed of metal-oxide-semiconductor gate stacks consisting of In0.53Ga0.47As /high-κ dielectric/5 nm TiN, for both Al2O3 and HfO2…”
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On the Electron and Hole Tunneling in a HfO2 Gate Stack With Extreme Interfacial-Layer Scaling by ANDO, Takashi, SATHAYE, Ninad D, MURALI, Kota V. R. M, CARTIER, Eduard A

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Interfacial layer optimization of high- k/metal gate stacks for low temperature processing by Linder, Barry P., Narayanan, Vijay, Cartier, Eduard A.

“…Understanding the requirements for obtaining high mobility gate stacks in a low temperature process is crucial for enabling a low temperature integration flow…”
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Crystallization of hafnium-oxide-based ferroelectrics for BEOL integration by Frank, Martin M., Cartier, Eduard A., Lavoie, Christian, Carr, Adra, Jordan-Sweet, Jean L., Jamison, Paul C., Gluschenkov, Oleg, Rozen, John, Narayanan, Vijay

“…We review the crystallization of hafnium-oxide-based ferroelectrics intended for back-end-of-line (BEOL) integration. We discuss furnace, rapid thermal, and…”
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Application of VRS Methodology for the Statistical Assessment of BTI in MG/HK CMOS Devices by Kerber, Andreas, Cartier, Eduard

“…Variability induced by bias temperature instability is an increasing concern in aggressively scaled CMOS technologies. To assess the stochastic nature of the…”
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Resistive Random Access Memory Filament Visualization and Characterization Using Photon Emission Microscopy by Stellari, Franco, Wu, Ernest Y., Ando, Takashi, Cartier, Eduard, Frank, Martin M., Cabral, Cyril, Song, Peilin, Pfeiffer, Dirk

“…Near InfraRed (NIR) photon emission is observed from filaments in HfO 2 Resistive Random Access Memories (ReRAMs). This technique is non-destructive and offers…”
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High Mobility High-Ge-Content SiGe PMOSFETs Using Al2O3/HfO2 Stacks With In-Situ O3 Treatment by Ando, Takashi, Hashemi, Pouya, Bruley, John, Rozen, John, Ogawa, Yohei, Koswatta, Siyuranga, Chan, Kevin K., Cartier, Eduard A., Mo, Renee, Narayanan, Vijay

“…We developed an Al 2 O 3 /HfO 2 bi-layer gate dielectric with an in-situ O 3 treatment for interface state density (D it ) and gate leakage current density (J…”
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Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With HfO2/TiN Gate Stacks by KERBER, Andreas, MAITRA, Kingsuk, MAJUMDAR, Amlan, HARGROVE, Mike, CARTIER, Eduard Albert

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The Impact of Self-Heating on Charge Trapping in High- k -Metal-Gate nFETs by Khan, Faraz, Cartier, Eduard, Kothandaraman, Chandrasekara, Scott, J. Campbell, Woo, Jason C. S., Iyer, Subramanian S.

“…In this letter, charge trapping behavior in 22-nm technology high-k -metal-gate SOI CMOS logic devices is analyzed under various bias stress and self-heating…”
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The Impact of Self-Heating on Charge Trapping in High-[Formula Omitted]-Metal-Gate nFETs by Khan, Faraz, Cartier, Eduard, Kothandaraman, Chandrasekara, Scott, J Campbell, Woo, Jason C S, Iyer, Subramanian S

“…In this letter, charge trapping behavior in 22-nm technology high-[Formula Omitted]-metal-gate SOI CMOS logic devices is analyzed under various bias stress and…”
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Evolution of interfacial Fermi level in In{sub 0.53}Ga{sub 0.47}As/high-κ/TiN gate stacks by Carr, Adra, Rozen, John, Frank, Martin M., Ando, Takashi, Cartier, Eduard A., Kerber, Pranita, Narayanan, Vijay, Haight, Richard

“…The net charge state was probed of metal-oxide-semiconductor gate stacks consisting of In{sub 0.53}Ga{sub 0.47}As /high-κ dielectric/5 nm TiN, for both Al{sub…”
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High Mobility High-Ge-Content SiGe PMOSFETs Using Al 2 O 3 /HfO 2 Stacks With In-Situ O 3 Treatment by Ando, Takashi, Hashemi, Pouya, Bruley, John, Rozen, John, Ogawa, Yohei, Koswatta, Siyuranga, Chan, Kevin K., Cartier, Eduard A., Mo, Renee, Narayanan, Vijay

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Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress by Cartier, E., Kerber, A.

“…The stress-induced leakage current (SILC) in nFETs with SiO 2 /HfO 2 /TiN dual-dielectric gate stacks with metal electrodes is studied during positive-bias…”
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