Search Results - "Cale, T. S."

Thermally induced stresses in 3D-IC inter-wafer interconnects: A combined grain-continuum and continuum approach by Bloomfield, M.O., Bentz, D.N., Lu, J.-Q., Gutmann, R.J., Cale, T.S.

“…We introduce a hybrid grain-continuum (HGC) approach to compute stresses in structures in which grain structures are important. We demonstrate the HGC approach…”
Get full text

Integrated multiscale process simulation by Cale, T.S., Bloomfield, M.O., Richards, D.F., Jansen, K.E., Gobbert, M.K.

“…We summarize two approaches to integrated multiscale process simulation (IMPS), particularly relevant to integrated circuit (IC) fabrication, in which models…”
Get full text

Texture and surface roughness of PRCVD aluminum films by YANG, D, JONNALAGADDA, R, ROGERS, B. R, HILLMAN, J. T, FOSTER, R. F, CALE, T. S

“…The effects of temperature, substrate type and diluent gas flow trajectories on the film growth rate, surface roughness, crystal orientation, grain size…”
Get full text

Substrate-independent sulfur-activated dielectric and barrier-layer surfaces to promote the chemisorption of highly polarizable metallorganics by SENKEVICH, J. J, YANG, G. R, TANG, F, WANG, G. C, LU, T. M, CALE, T. S, JEZEWSKI, C, LANFORD, W. A

Get full text

Plasma processes in microelectronic device manufacturing by Rogers, B.R., Cale, T.S.

“…Plasma processes are an important part of integrated circuit (IC) fabrication. Their wide use can be attributed to the increased requirements of fabricating…”
Get full text

Effects of carrier film physical properties on W CMP by WANG, D, ZUTSHI, A, BIBBY, T, BEAUDOIN, S. P, CALE, T. S

“…The roughness, displacement under load, and thickness of 28 carrier films have been measured and their effects on polishing non-uniformity (NU) and removal…”
Get full text

Modeling and simulation of plasma enhanced processing for integrated circuit fabrication by Prasad, V., Bloomfield, M.O., Richards, D.F., Liang, H., Cale, T.S.

“…Plasma processes are used extensively in deposition and etching operations used in the fabrication of integrated circuits (ICs). Modeling and simulation…”
Get full text

Deposition and etch processes: continuum film evolution in microelectronics by Cale, T.S., Rogers, B.R., Merchant, T.P., Borucki, L.J.

“…Aspects of modeling and simulation of topography evolution during deposition and etch processes used in the fabrication of integrated circuits are discussed…”
Get full text

Step coverage prediction in low-pressure chemical vapor deposition by Raupp, Gregory B, Cale, T. S

Get full text

Ballistic transport‐reaction prediction of film conformality in tetraethoxysilane O2 plasma enhanced deposition of silicon dioxide by Cale, T. S., Raupp, G. B., Gandy, T. H.

“…EVOLVE, a low pressure deposition process simulator based on a fundamental model for free molecular transport and heterogeneous surface reactions in features,…”
Get full text

Improving electromigration reliability in Al-alloy lines by Rajagopalan, G., Dreyer, M.L., Theodore, N.D., Cale, T.S.

“…We present a method that utilizes surface topography to control the distribution of grain sizes, single grain segment lengths and polygrain cluster lengths in…”
Get full text

Material removal model for chemical–mechanical polishing considering wafer flexibility and edge effects by Seok, Jongwon, Sukam, Cyriaque P., Kim, Andrew T., Tichy, John A., Cale, Timothy S.

“…This paper describes a two-dimensional, multiscale, material removal model for chemical–mechanical planarization that includes: (i) asperity deformation; (ii)…”
Get full text

Stress distribution in chemical mechanical polishing by Srinivasa-Murthy, C, Wang, D, Beaudoin, S.P, Bibby, T, Holland, K, Cale, T.S

“…This paper describes a first principles, three-dimensional, wafer scale model that relates chemical mechanical polishing (CMP) non-uniformity (NU) to the…”
Get full text

A fundamental feature scale model for low pressure deposition processes by Cale, T. S., Gandy, T. H., Raupp, G. B.

“…The integro‐differential equations which govern free molecular flow and low pressure chemical vapor deposition in long rectangular trenches are reviewed. The…”
Get full text

Influences of grain structure on thermally induced stresses in 3D IC inter-wafer vias by Bentz, D. N., Bloomfield, M. O., Lu, J.-Q, Gutmann, R. J., Cale, T. S.

“…We discuss the development of a grain-continuum model to examine the effects of thermally induced stress in 3D IC inter-wafer vias. We demonstrate the approach…”
Get full text

A unified line‐of‐sight model of deposition in rectangular trenches by Cale, T. S., Raupp, G. B.

“…The integro‐differential equations which describe free molecular flow in long rectangular trenches in the absence of deposition and to both low pressure…”
Get full text

A computational framework for modelling grain-structure evolution in three dimensions by Bloomfield, Max O., Richards, David F., Cale†, Timothy S.

“…We describe a simulation framework designed to track individual grains in a material during simulations of formation, processing and usage. The framework,…”
Get full text

Size effect on magnetic moment density of dispersed nickel by CALE, T. S, RICHARDSON, J. T, GINESTRA, J

“…An extension of superparamagnetic superposition analysis is used to show a crystallite size effect on the magnetic moment density of nickel dispersed on…”
Get full text

Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform by Pozder, S., Lu, J.-Q., Kwon, Y., Zollner, S., Yu, J., McMahon, J.J., Cale, T.S., Yu, K., Gutmann, R.J.

“…A previously proposed wafer-level 3D IC technology platform has been extensively evaluated for compatibility with conventional IC packaging. Results…”
Get full text

Free molecular transport and deposition in cylindrical features by Cale, T. S., Raupp, G. B.

“…A Clausing‐like integral equation is derived which applies to both low pressure chemical vapor deposition (CVD) and physical vapor deposition (PVD) in…”
Get full text