Search Results - "COTEUS, Paul W"

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  1. 1

    The IBM Blue Gene/Q Compute Chip by Haring, Ruud A., Ohmacht, Martin, Fox, Thomas W., Gschwind, Michael K., Satterfield, David L., Sugavanam, Krishnan, Coteus, Paul W., Heidelberger, Philip, Blumrich, Matthias A., Wisniewski, Robert W., Gara, Alan, Chiu, George Liang-Tai, Boyle, Peter A., Chist, Norman H., Changhoan Kim

    Published in IEEE MICRO (01-03-2012)
    “…Blue Gene/Q aims to build a massively parallel high-performance computing system out of power-efficient processor chips, resulting in power-efficient,…”
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    Journal Article
  2. 2

    Practical Strategies for Power-Efficient Computing Technologies by Chang, Leland, Frank, David J., Montoye, Robert K., Koester, Steven J., Ji, Brian L., Coteus, Paul W., Dennard, Robert H., Haensch, Wilfried

    Published in Proceedings of the IEEE (01-02-2010)
    “…After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by…”
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    Journal Article
  3. 3

    An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme by Kyu-hyoun Kim, Hoe-Ju Chung, Woo-Seop Kim, Moonsook Park, Jang, Y.-C., Jin-Young Kim, Hwan-Wook Park, Uksong Kang, Coteus, P.W., Joo Sun Choi, Changhyun Kim

    Published in IEEE journal of solid-state circuits (01-01-2007)
    “…This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme…”
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    Journal Article Conference Proceeding
  4. 4

    Frequency-dependent losses on high-performance interconnections by Deutsch, A., Kopcsay, G.V., Coteus, P.W., Surovic, C.W., Dahlen, P.E., Heckmann, D.L., Dah-Weih Duan

    “…This paper compares the major classes of chip-to-chip and on-chips interconnections used in high-performance computers and communication systems and reviews…”
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    Journal Article
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    When are transmission-line effects important for on-chip interconnections? by Deutsch, A., Kopcsay, G.V., Restle, P.J., Smith, H.H., Katopis, G., Becker, W.D., Coteus, P.W., Surovic, C.W., Rubin, B.J., Dunne, R.P., Gallo, T., Jenkins, K.A., Terman, L.M., Dennard, R.H., Sai-Halasz, G.A., Krauter, B.L., Knebel, D.R.

    “…Short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m are analyzed in a five-metal-layer structure. We study capacitive…”
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    Journal Article
  7. 7

    A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator by Kim, Kyu-hyoun, Coteus, Paul W., Dreps, Daniel, Kim, Seongwon, Rylov, Sergey V., Friedman, Daniel J.

    “…In this paper, a wide frequency open-loop quadrature generator is sufficiently compact to allow many stages to be cascaded affordably. The generator is built…”
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    Conference Proceeding
  8. 8

    Characterization and performance evaluation of differential shielded cables for multi-Gb/s data-rates by Deutsch, A., Kopcsay, G.V., Surovic, C.W., Coteus, P.W., Lanzetta, A.P., Takken, T., Bond, P.W.

    Published in IEEE transactions on advanced packaging (01-02-2002)
    “…This paper compares several differential cable characteristics that were evaluated for multi-Gb/s data-rates for both data and clock paths for 1-10 m lengths…”
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    Journal Article
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    Electrical characteristics of high-performance pin-in-socket and pad-on-pad connectors by Deutsch, A., Surovic, C.W., Campbell, J.S., Coteus, P.W., Lanzetta, A.P., Holton, J.T., Knight, A.D.

    “…Two types of high-performance, high-density connectors, pin-in-socket, and pad-on-pad, are investigated for providing many hundreds of signal contacts in…”
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    Journal Article
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