Search Results - "CHO, Hoosung"
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Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory
Published in 2009 Symposium on VLSI Technology (01-06-2009)“…Vertical NAND flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical…”
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Conference Proceeding
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A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure
Published in IEEE journal of solid-state circuits (01-01-2009)“…A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is…”
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Journal Article Conference Proceeding -
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Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node
Published in 2006 International Electron Devices Meeting (2006)“…For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S 3 (single-crystal Si layer stacking) technology, which was…”
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Conference Proceeding -
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A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure
Published in 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers (01-02-2008)“…Recently, 3-dimensional (3D) memories have regained attention as a potential future memory solution featuring low cost, high density and high performance. We…”
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Conference Proceeding -
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65nm high performance SRAM technology with 25F2 0.16/spl mu/m/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications
Published in Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005 (2005)“…For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and…”
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Conference Proceeding -
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Highly cost effective and high performance 65nm S/sup 3/ (stacked single-crystal Si) SRAM technology with 25F/sup 2/, 0.16um/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications
Published in Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005 (2005)“…In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell,…”
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Conference Proceeding -
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Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM
Published in IEEE International Electron Devices Meeting 2003 (2003)“…The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer…”
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Conference Proceeding -
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Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM
Published in IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 (2004)“…For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose…”
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Conference Proceeding -
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