Search Results - "CHANG, Leland"

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches by Chang, L., Montoye, R.K., Nakamura, Y., Batson, K.A., Eickemeyer, R.J., Dennard, R.H., Haensch, W., Jamsek, D.

“…An eight-transistor (8T) cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. While the cell itself can be…”
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Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs) by Yoonmyung Lee, Daeyeon Kim, Jin Cai, Lauer, Isaac, Chang, Leland, Koester, Steven J., Blaauw, David, Sylvester, Dennis

“…The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF…”
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POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators by Venkataramani, Swagath, Jungwook Choi, Srinivasan, Vijayalakshmi, Gopalakrishnan, Kailash, Leland Chang

“…The growing prominence and computational challenges imposed by Deep Neural Networks (DNNs) has fueled the design of specialized accelerator architectures and…”
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Extremely scaled silicon nano-CMOS devices by Chang, L., Yang-kyu Choi, Ha, D., Ranade, P., Shiying Xiong, Bokor, J., Chenming Hu, King, T.J.

“…Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator…”
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CMOS circuit performance enhancement by surface orientation optimization by Chang, L., Leong, M., Yang, M.

“…With the advent of novel device structures that can be easily fabricated outside of the traditional (100) plane, it may be advantageous to change the crystal…”
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Sub-50 nm P-channel FinFET by Xuejue Huang, Wen-Chin Lee, Kuo, C., Hisamoto, D., Leland Chang, Kedzierski, J., Anderson, E., Takeuchi, H., Yang-Kyu Choi, Asano, K., Subramanian, V., Tsu-Jae King, Bokor, J., Chenming Hu

“…High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel…”
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Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs by Leland Chang, Yang, K.J., Yee-Chia Yeo, Polishchuk, I., Tsu-Jae King, Chenming Hu

“…The impact of energy quantization on gate tunneling current is studied for double-gate and ultrathin body MOSFETs. Reduced vertical electric field and quantum…”
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A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation by Ditlow, G S, Montoye, R K, Storino, S N, Dance, S M, Ehrenreich, S, Fleischer, B M, Fox, T W, Holmes, K M, Mihara, J, Nakamura, Y, Onishi, S, Shearer, R, Wendel, D, Leland Chang

“…In multi-ported register files, memory cell size grows quadratically with the total number of ports due to wordline and bitline wiring. Reducing the number of…”
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FinFET scaling to 10 nm gate length by Bin Yu, Leland Chang, Ahmed, S., Haihong Wang, Bell, S., Chih-Yuh Yang, Tabery, C., Chau Ho, Qi Xiang, Tsu-Jae King, Bokor, J., Chenming Hu, Ming-Ren Lin, Kyser, D.

“…While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential…”
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Operational Amplifier Based Test Structure for Quantifying Transistor Threshold Voltage Variation by Ji, B.L., Pearson, D.J., Lauer, I., Stellari, F., Frank, D.J., Chang, L., Ketchen, M.B.

“…A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage…”
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Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems by Rajendran, B., Yong Liu, Jae-sun Seo, Gopalakrishnan, K., Chang, Leland, Friedman, D. J., Ritter, M. B.

“…The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic…”
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Efficient AI System Design With Cross-Layer Approximate Computing by Venkataramani, Swagath, Sun, Xiao, Wang, Naigang, Chen, Chia-Yu, Choi, Jungwook, Kang, Mingu, Agarwal, Ankur, Oh, Jinwook, Jain, Shubham, Babinsky, Tina, Cao, Nianzheng, Fox, Thomas, Fleischer, Bruce, Gristede, George, Guillorn, Michael, Haynie, Howard, Inoue, Hiroshi, Ishizaki, Kazuaki, Klaiber, Michael, Lo, Shih-Hsien, Maier, Gary, Mueller, Silvia, Scheuermann, Michael, Ogawa, Eri, Schaal, Marcel, Serrano, Mauricio, Silberman, Joel, Vezyrtzis, Christos, Wang, Wei, Yee, Fanchieh, Zhang, Jintao, Ziegler, Matthew, Zhou, Ching, Ohara, Moriyoshi, Lu, Pong-Fei, Curran, Brian, Shukla, Sunil, Srinivasan, Vijayalakshmi, Chang, Leland, Gopalakrishnan, Kailash

“…Advances in deep neural networks (DNNs) and the availability of massive real-world data have enabled superhuman levels of accuracy on many AI tasks and ushered…”
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BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks by Jain, Shubham, Venkataramani, Swagath, Srinivasan, Vijayalakshmi, Choi, Jungwook, Gopalakrishnan, Kailash, Chang, Leland

“…Fixed-point implementations (FxP) are prominently used to realize Deep Neural Networks (DNNs) efficiently on energy-constrained platforms. The choice of…”
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Operational amplifier based test structure for transistor threshold voltage variation by Ji, B.L., Pearson, D.J., Lauer, I., Stellari, F., Frank, D.J., Chang, L., Ketchen, M.B.

“…A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage…”
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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling by Lee, Sae Kyu, Agrawal, Ankur, Silberman, Joel, Ziegler, Matthew, Kang, Mingu, Venkataramani, Swagath, Cao, Nianzheng, Fleischer, Bruce, Guillorn, Michael, Cohen, Matthew, Mueller, Silvia M., Oh, Jinwook, Lutz, Martin, Jung, Jinwook, Koswatta, Siyu, Zhou, Ching, Zalani, Vidhi, Kar, Monodeep, Bonanno, James, Casatuta, Robert, Chen, Chia-Yu, Choi, Jungwook, Haynie, Howard, Herbert, Alyssa, Jain, Radhika, Kim, Kyu-Hyoun, Li, Yulong, Ren, Zhibin, Rider, Scot, Schaal, Marcel, Schelm, Kerstin, Scheuermann, Michael R., Sun, Xiao, Tran, Hung, Wang, Naigang, Wang, Wei, Zhang, Xin, Shah, Vinay, Curran, Brian, Srinivasan, Vijayalakshmi, Lu, Pong-Fei, Shukla, Sunil, Gopalakrishnan, Kailash, Chang, Leland

“…Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm…”
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Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC by Kar, Monodeep, Silberman, Joel, Venkataramani, Swagath, Srinivasan, Viji, Fleischer, Bruce, Rubin, Joshua, Lancaster, JohnDavid, Lee, Saekyu, Cohen, Matthew, Ziegler, Matthew, Cao, Nianzheng, Woodward, Sandra, Agrawal, Ankur, Zhou, Ching, Chatarasi, Prasanth, Gooding, Thomas, Guillorn, Michael, Hekmatshoartabari, Bahman, Jacob, Philip, Jain, Radhika, Jain, Shubham, Jung, Jinwook, Kim, Kyu-Hyoun, Koswatta, Siyu, Lutz, Martin, Mannari, Alberto, Mathew, Abey K., Nair, Indira, Ranjan, Ashish, Ren, Zhibin, Rider, Scot, Rower, Thomas, Satterfield, David, Schaal, Marcel, Sen, Sanchari, Tellez, Gustavo, Tran, Hung, Wang, Wei, Zalani, Vidhi, Zhang, Jintao, Zhang, Xin, Shah, Vinay, Senger, Robert, Kumar, Arvind, Lu, Pong-Fei, Chang, Leland

“…Discrete AI inference cards, operating under form-factor and system-defined peak power constraints, must serve diverse inference requests with widely varying…”
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Moore's law lives on [CMOS transistors] by Leland Chang, Yang-Kyu Choi, Kedzierski, J., Lindert, N., Peiqi Xuan, Bokor, J., Chenming Hu, Tsu-Jae King

“…We discuss several device structures suitable for scaling CMOS devices well into the nano-CMOS era, perhaps down below 10 nm physical gate length. The…”
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A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering by Suyoung Bang, Jae-sun Seo, Chang, Leland, Blaauw, David, Sylvester, Dennis

“…In this work, a switched-capacitor voltage regulator (SCVR) that dithers flying capacitance to reduce output voltage ripple is presented, and the benefits of…”
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DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator by Venkataramani, Swagath, Choi, Jungwook, Srinivasan, Vijayalakshmi, Wang, Wei, Zhang, Jintao, Schaal, Marcel, Serrano, Mauricio J., Ishizaki, Kazuaki, Inoue, Hiroshi, Ogawa, Eri, Ohara, Moriyoshi, Chang, Leland, Gopalakrishnan, Kailash

“…The ubiquitous adoption of systems specialized for AI requires bridging two seemingly conflicting challenges—the need to deliver extreme processing…”
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A 512kb 8T SRAM Macro Operating Down to 0.57V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45nm SOI CMOS by Qazi, Masood, Stawiasz, Kevin, Chang, Leland, Chandrakasan, Anantha P

“…An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2 V down to 0.57 V with access times from 400 ps to 3.4 ns. Timing variation…”
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