Search Results - "CASSE, Mikael"

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K by Mariniello, Genaro, Barraud, Sylvain, Vinet, Maud, Cassé, Mikael, Faynot, Olivier, Calcade, Jaime, Antonio Pavanello, Marcelo

“…•The impact higher temperatures are noticed by the increase of Ioff and the decrease of Ion, on stacked vertically nanowire devices.•The reduction of μr…”
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Electrical characterization of stacked SOI nanowires at low temperatures by Rodrigues, Jaime C., Mariniello, Genaro, Cassé, Mikael, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo A.

“…[Display omitted] This work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature…”
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Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures by Prates, Rhaycen R., Barraud, Sylvain, Casse, Mikael, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo A.

“…This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar…”
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Ultra-Low-Voltage UTBB-SOI-Based, Pseudo-Static Storage Circuits for Cryogenic CMOS Applications by Nibhanupudi, S. S. Teja, Sundara Raman, Siddhartha Raman, Casse, Mikael, Hutin, Louis, Kulkarni, Jaydeep P.

“…Operating CMOS circuits at cryogenic temperatures offers advantages of higher mobility, higher ON-current, and better subthreshold characteristics, which can…”
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Mobility comparison between front and back channels in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors by the front-gate split capacitance-voltage method by Ohata, Akiko, Cristoloveanu, Sorin, Cassé, Mikael

“…The mobilities of the front and back channels in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistors with a thin (2nm) gate oxide…”
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On the mobility in high- κ/metal gate MOSFETs: Evaluation of the high- κ phonon scattering impact by Weber, Olivier, Cassé, Mikael, Thevenod, Laurent, Ducroquet, Frédérique, Ernst, Thomas, Deleonibus, Simon

“…We report an experimental study of the mobility in TiN/HfO 2 gate stacks focused on the accurate determination of the HfO 2 remote soft phonon scattering…”
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Low-field Mobility Degradation Factors Temperature Dependence in Two-level Stacked Nanowire MOSFETs from 120K to 400K by Rodrigues, Jaime Calcade, Casse, Mikael, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, Pavanello, Marcelo Antonio

“…This study investigates carrier mobility and its degradation factors as a function of temperature for 2-level stacked nanowire MOSFETs in the temperature range…”
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Evidence of 2D intersubband scattering in thin film fully depleted silicon-on-insulator transistors operating at 4.2 K by Cassé, Mikaël, Cardoso Paz, Bruna, Ghibaudo, Gérard, Poiroux, Thierry, Vincent, Emmanuel, Galy, Philippe, Juge, André, Gaillard, Fred, de Franceschi, Silvano, Meunier, Tristan, Vinet, Maud

“…We report the observation at low temperature of a hump in the linear transfer characteristic of a thin film fully depleted silicon-on-insulator transistor when…”
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Electrical Characterization of Ω-Gate Nanowire MOSFETs Down to Cryogenic Temperatures by Matos, Jefferson Almeida, de Souza, Michelly, Casse, Mikael, Barraud, Sylvain, Faynot, Olivier, Pavanello, Marcelo A.

“…This work presents the electrical characterization of Ω-gate SOI nanowire MOSFETs in the temperature range from 82 K to 330 K. Devices with different fin…”
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Extraction of Drain Current Variability Components in Junctionless Nanowire Transistors by da Silva, Lucas Mota Barbosa, Pavanello, Marcelo Antonio, Casse, Mikael, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, de Souza, Michelly

“…This work investigates the applicability of a recent drain current mismatch model developed for inversion mode FDSOI transistors to junctionless nanowire…”
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Analysis of Variability in Transconductance and Mobility of Nanowire Transistors by Barbosa da Silva, Lucas Mota, Pavanello, Marcelo Antonio, Casse, Mikael, Barraud, Sylvain, Vinet, Maud, Faynot, Olivier, de Souza, Michelly

“…This work presents a comparison between the variability in junctionless nanowire transistors and inversion-mode nanowire transistors, looking at the…”
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On the Zero Temperature Coefficient in FD-SOI MOSFETs by Catapano, Edoardo, Mota Frutuoso, Tadeu, Casse, Mikael, Gérard, Ghibaudo

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Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width by Coquand, R., Casse, M., Barraud, S., Cooper, D., Maffini-Alvaro, V., Samson, M., Monfray, S., Boeuf, F., Ghibaudo, G., Faynot, O., Poiroux, T.

“…A detailed study of performance in uniaxially strained Si nanowire (NW) transistors fabricated by lateral strain relaxation of biaxial strained-SOI (sSOI)…”
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Experimental Investigation of Hole Transport in Strained Si1―xGex/SOI pMOSFETs: Part II—Mobility and High-Field Transport in Nanoscaled PMOS by CASSE, Mikaël, HUTIN, Louis, LE ROYER, Cyrille, COOPER, David, HARTMANN, Jean-Michel, REIMBOLD, Gilles

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Experimental Investigation of the Tunneling Injection Boosters for Enhanced ION ETSOI Tunnel FET by VILLALON, Anthony, LE ROYER, Cyrille, CASSE, Mikaël, COOPER, David, HARTMANN, Jean-Michel, ALLAIN, Fabienne, TABONE, Claude, ANDRIEU, François, CRISTOLOVEANU, Sorin

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Cryogenic L-UTSOI model for 22nm pMOS FD-SOI, including stress effects by Alepidis, Miltiadis, Jarjayes, Sylvie, Bedecarrats, Thomas, Martinie, Sebastien, Casse, Mikael, Witt, Christian, Rozeau, Olivier

“…In this paper, we explore the effect of mechanical stress on the electrical parameters, for the first time at cryogenic temperatures, using L-UTSOI 102.7…”
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Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors by De Souza, Michelly, Barraud, Sylvain, Casse, Mikael, Vinet, Maud, Faynor, Olivier, Pavanello, Marcelo Antonio

“…In this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire n MOS transistors is presented…”
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Experimental Evaluation of 7-Level Stacked Nanosheet SOI MOSFETs Analog Parameters by Souza, Michelly De, Rodrigues, Jaime Calcade, Silva, Lucas Mota Barbosa Da, Bergamaschi, Flavio Enrico, Casse, Mikael, Barraud, Sylvain, Faynot, Olivier, Pavanello, Marcelo Antonio

“…This study assesses the analog parameters of 7-level stacked SOI nanosheet transistors. The impact of nanosheet width, channel length, and bias condition is…”
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A New Method for Series Resistance Extraction of Nanometer MOSFETs by Trevisoli, Renan, Trevisoli Doria, Rodrigo, de Souza, Michelly, Barraud, Sylvain, Vinet, Maud, Casse, Mikael, Reimbold, Gilles, Faynot, Olivier, Ghibaudo, Gerard, Pavanello, Marcelo Antonio

“…This paper presents a new method for the series resistance extraction in ultimate MOSFETs using a single drain current versus gate voltage characteristic…”
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Experimental Investigation of Hole Transport in Strained \hbox\hbox/\hbox pMOSFETs-Part I: Scattering Mechanisms in Long-Channel Devices by Casse, M., Hutin, L., Le Royer, C., Cooper, D., Hartmann, J., Reimbold, G.

“…This paper presents a wide experimental study of hole transport in SiGe pMOSFETs. Various Ge contents, from 20% up to 60%, and growth templates [unstrained or…”
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