Search Results - "C.R. Manoj"

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  1. 1

    BoostedDim attention: A novel data-driven approach to improving LiDAR-based lane detection by Omkar Patil, Binoy B. Nair, Rajat Soni, Arunkrishna Thayyilravi, C.R. Manoj

    Published in Ain Shams Engineering Journal (01-09-2024)
    “…Lane detection is a fundamental component of advanced driver assistance systems, facilitating critical functionalities like Lane Keep/Change Assistance, Lane…”
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    Journal Article
  2. 2

    Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization by Sachid, A.B., Manoj, C.R., Sharma, D.K., Rao, V.R.

    Published in IEEE electron device letters (01-01-2008)
    “…The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate…”
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    Journal Article
  3. 3

    Impact of High- k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs by Manoj, C.R., Rao, V.R.

    Published in IEEE electron device letters (01-04-2007)
    “…The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of…”
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    Journal Article
  4. 4

    Device Design and Optimization Considerations for Bulk FinFETs by Manoj, C.R., Nagpal, M., Varghese, D., Rao, V.R.

    Published in IEEE transactions on electron devices (01-02-2008)
    “…Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using…”
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    Journal Article
  5. 5

    Understanding and Optimization of Hot-Carrier Reliability in Germanium-on-Silicon pMOSFETs by Maji, D., Crupi, F., Amat, E., Simoen, E., De Jaeger, B., Brunco, D.P., Manoj, C.R., Rao, V.R., Magnone, P., Giusi, G., Pace, C., Pantisano, L., Mitard, J., Rodriguez, R., Nafria, M.

    Published in IEEE transactions on electron devices (01-05-2009)
    “…In this paper, a comprehensive study of hot- carrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate…”
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    Journal Article
  6. 6

    Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs by Manoj, C.R., Sachid, A.B., Feng Yuan, Chang-Yun Chang, Rao, V.R.

    Published in IEEE electron device letters (01-01-2010)
    “…In this letter, we report the enhanced fringe capacitance in FinFETs when compared to the equivalent planar MOSFETs at the 22-nm node. We show that this…”
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    Journal Article
  7. 7

    Implications of fin width scaling on variability and reliability of high-k metal gate FinFETs by Chabukswar, S., Maji, D., Manoj, C.R., Anil, K.G., Rao, V. Ramgopal, Crupi, F., Magnone, P., Giusi, G., Pace, C., Collaert, N.

    Published in Microelectronic engineering (01-10-2010)
    “…In this paper, we report a study to understand the fin width dependence on performance, variability and reliability of n-type and p-type triple-gate fin field…”
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    Journal Article
  8. 8

    Improving the DC performance of Bulk FinFETs by Optimum Body Doping by Manoj, C.R., Nagpal, M., Ramgopal Rao, V.

    “…It is shown that body doping can be used to match the Bulk FinFETs' DC performance with that of SOI FinFETs, even down to 22 nm technology node, by using…”
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    Conference Proceeding
  9. 9

    Parasitics effects in multi gate MOSFETs by Manoj, C.R., Mangal, A., Rao, V.R., Tsutsui, K., Iwai, H.

    Published in 2006 International Workshop on Nano CMOS (01-01-2006)
    “…The parasitics in multi-gate transistors (MugFETs or FinFETs) are expected to significantly degrade the device and circuit performance in scaled technologies…”
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    Conference Proceeding