Highly reliable vertical NAND technology with biconcave shaped storage layer and leakage controllable offset structure

The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resista...

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Bibliographic Details
Published in:	2010 Symposium on VLSI Technology pp. 173 - 174
Main Authors:	Won-seok Cho, Sun Il Shim, Jaehoon Jang, Hoo-sung Cho, Byoung-Koan You, Byoung-Keun Son, Ki-hyun Kim, Jae-Joo Shim, Choul-min Park, Jin-soo Lim, Kyoung-Hoon Kim, De-will Chung, Ju-Young Lim, Hui-Chang Moon, Sung-min Hwang, Hyun-seok Lim, Han-Soo Kim, Jungdal Choi, Chilhee Chung
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-06-2010
Subjects:	CTF Flash memory Leakage current Logic gates Resistance TCAT Transistors Tungsten Vertical
Online Access:	Get full text
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Summary:	The performance and reliability of 3-D NAND cells fabricated by TCAT (Terabit Cell Array Transistor) technology have been improved significantly via a damascened metal gates and a controlled offset between BL contact and select transistor. The damascened metal gate providing sufficiently low resistance is achieved by adopting a novel metal process. Highly suppressed disturbance property is achieved by the appropriate offset which reduces the leakage current through the select transistor. It is proved that the TCAT NAND is a manufacturable technology in terms of reliability as well as performance in a channel hole with a diameter of 90nm.
ISBN:	9781424454518 1424454514
ISSN:	0743-1562
DOI:	10.1109/VLSIT.2010.5556216