Search Results - "Bulzacchelli, John F"

A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology by Chakraborty, Sudipto, Frank, David J., Tien, Kevin, Rosno, Pat, Yeck, Mark, Glick, Joseph A., Robertazzi, Raphael, Richetta, Ray, Bulzacchelli, John F., Underwood, Devin, Ramirez, Daniel, Yilma, Dereje, Davies, Andrew, Joshi, Rajiv V., Chambers, Shawn D., Lekuch, Scott, Inoue, Ken, Wisnieff, Dorothy, Baks, Christian W., Bethune, Donald S., Timmerwilke, John, Fox, Thomas, Song, Peilin, Johnson, Blake R., Gaucher, Brian P., Friedman, Daniel J.

“…A scalable, non-multiplexed cryogenic 14-nm FinFET quantum bit (qubit) state controller (QSC) for use in the semi-autonomous control of superconducting…”
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Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS by Perez, Miguel E., Sperling, Michael A., Bulzacchelli, John F., Toprak-Deniz, Zeynep, Diemoz, Timothy E.

“…A distributed network of low-dropout (LDO) microregulators (uREGs) senses and corrects the voltages at multiple points on a power supply grid in a multi-core…”
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A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS by Toprak-Deniz, Zeynep, Proesel, Jonathan E., Bulzacchelli, John F., Ainspan, Herschel A., Dickson, Timothy O., Beakes, Michael P., Meghelli, Mounir

“…This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter (TX) implemented in a 14-nm CMOS FinFET technology. Equalization is…”
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A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS by Proesel, Jonathan E., Toprak-Deniz, Zeynep, Cevrero, Alessandro, Ozkaya, Ilter, Kim, Seongwon, Kuchta, Daniel M., Lee, Sungjae, Rylov, Sergey V., Ainspan, Herschel, Dickson, Timothy O., Bulzacchelli, John F., Meghelli, Mounir

“…This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk…”
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A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links by Dickson, Timothy O., Deniz, Zeynep Toprak, Cochet, Martin, Beukema, Troy J., Kossel, Marcel, Morf, Thomas, Choi, Young-Ho, Francese, Pier Andrea, Brandli, Matthias, Baks, Christian W., Proesel, Jonathan E., Bulzacchelli, John F., Beakes, Michael P., Yoo, Byoung-Joo, Ahn, Hyoungbae, Lim, Dong-Hyuk, Kang, Gunil, Park, Sang-Hune, Meghelli, Mounir, Rhew, Hyo Gyuem, Friedman, Daniel J., Choi, Michael, Soyuer, Mehmet, Shin, Jongshin

“…This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline…”
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A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks by Rylyakov, Alexander, Proesel, Jonathan E., Rylov, Sergey, Lee, Benjamin G., Bulzacchelli, John F., Ardey, Abhijeet, Parker, Ben, Beakes, Michael, Baks, Christian W., Schow, Clint L., Meghelli, Mounir

“…We report a dc-coupled burst-mode (BM) receiver for optical links in a dynamically reconfigurable network. Through the introduction of interlocking search…”
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Errata - Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS" by Toprak-Deniz, Zeynep, Proesel, Jonathan E., Bulzacchelli, John F., Ainspan, Herschel A., Dickson, Timothy O., Beakes, Michael P., Meghelli, Mounir

“…In the above-named work, the photograph that appeared next to the author, Herschel A. Ainspan, was not an image of this author and was published in error. No…”
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Equalization for Electrical Links: Current Design Techniques and Future Directions by Bulzacchelli, John F.

“…Another article in this issue, the introductory article by Tony Chan Carusone, discussed how the limited bandwidth of an electrical channel causes distortion…”
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A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology by Bulzacchelli, J. F., Menolfi, C., Beukema, T. J., Storaska, D. W., Hertle, J., Hanson, D. R., Ping-Hsuan Hsieh, Rylov, S. V., Furrer, D., Gardellini, D., Prati, A., Morf, T., Sharma, V., Kelkar, R., Ainspan, H. A., Kelly, W. R., Chieco, L. R., Ritter, G. A., Sorice, J. A., Garlett, J. D., Callan, R., Brandli, M., Buchmann, P., Kossel, M., Toifl, T., Friedman, D. J.

“…This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes…”
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A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS by Agrawal, A., Bulzacchelli, J. F., Dickson, T. O., Liu, Y., Tierno, J. A., Friedman, D. J.

“…This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward equalizer (FFE) and 5-tap decision-feedback equalizer (DFE),…”
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Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage by Bulzacchelli, J. F., Toprak-Deniz, Z., Rasmus, T. M., Iadanza, J. A., Bucossi, W. L., Seongwon Kim, Blanco, R., Cox, C. E., Chhabra, M., LeBlanc, C. D., Trudeau, C. L., Friedman, D. J.

“…A dual-loop architecture employs eight distributed microregulators (UREGs) to achieve load response times below 500 ps in 45-nm SOI CMOS. The trip point of an…”
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A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology by Frank, David J., Chakraborty, Sudipto, Tien, Kevin, Rosno, Pat, Fox, Thomas, Yeck, Mark, Glick, Joseph A., Robertazzi, Raphael, Richetta, Ray, Bulzacchelli, John F., Ramirez, Daniel, Yilma, Dereje, Davies, Andrew, Joshi, Rajiv V., Chambers, Shawn D., Lekuch, Scott, Inoue, Ken, Underwood, Devin, Wisnieff, Dorothy, Baks, Chris, Bethune, Donald, Timmerwilke, John, Johnson, Blake R., Gaucher, Brian P., Friedman, Daniel J.

“…Error-corrected quantum computing is expected to require at least 10 5 to 10 6 physical qubits. Superconducting transmons, which are promising qubit candidates…”
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An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects by Dickson, T. O., Yong Liu, Rylov, S. V., Bing Dang, Tsang, C. K., Andry, P. S., Bulzacchelli, J. F., Ainspan, H. A., Xiaoxiong Gu, Turlapati, L., Beakes, M. P., Parker, B. D., Knickerbocker, J. U., Friedman, D. J.

“…A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging…”
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Using Cryogenic CMOS Control Electronics to Enable a Two-Qubit Cross-Resonance Gate by Underwood, Devin, Glick, Joseph A., Inoue, Ken, Frank, David J., Timmerwilke, John, Pritchett, Emily, Chakraborty, Sudipto, Tien, Kevin, Yeck, Mark, Bulzacchelli, John F., Baks, Chris, Robertazzi, Raphael, Beck, Matthew, Joshi, Rajiv V., Wisnieff, Dorothy, Lekuch, Scott, Gaucher, Brian P., Friedman, Daniel J., Rosno, Pat, Ramirez, Daniel, Ruedinger, Jeff

“…Qubit control electronics composed of CMOS circuits are of critical interest for next-generation quantum computing systems. A CMOS-based application-specific…”
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A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology by Bulzacchelli, J.F., Meghelli, M., Rylov, S.V., Rhee, W., Rylyakov, A.V., Ainspan, H.A., Parker, B.D., Beakes, M.P., Aichin Chung, Beukema, T.J., Pepeljugoski, P.K., Shan, L., Kwark, Y.H., Gowda, S., Friedman, D.J.

“…This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap…”
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A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology by Dickson, T.O., Bulzacchelli, J.F., Friedman, D.J.

“…The design and experimental results of a low-power, low-area 5-tap decision feedback equalizer (DFE) implemented in a 45 nm SOI CMOS technology are reported…”
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Low power cryogenic RF ASICs for quantum computing by Frank, David J., Chakraborty, Sudipto, Tien, Kevin, Rosno, Pat, Yeck, Mark, Glick, Joseph A., Robertazzi, Raphael, Richetta, Ray, Bulzacchelli, John F., Ramirez, Daniel, Yilma, Dereje, Davies, Andrew, Joshi, Rajiv V., Lekuch, Scott, Inoue, Ken, Underwood, Devin, Wisnieff, Dorothy, Baks, Chris, Timmerwilke, John, Song, Peilin, Johnson, Blake R., Gaucher, Brian P., Friedman, Daniel J.

“…Quantum computing is a promising new approach to computing that may allow the solution of certain problems that are very difficult to solve on classical…”
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An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS by Yonar, A. Serdar, Francese, Pier Andrea, Brandli, Matthias, Kossel, Marcel, Morf, Thomas, Proesel, Jonathan E., Rylov, Sergey, Ainspan, Herschel, Cochet, Martin, Deniz, Zeynep, Dickson, Timothy, Beukema, Troy, Baks, Christian, Beakes, Michael, Bulzacchelli, John F., Choi, Young-Ho, Yoo, Byoung-Joo, Ahn, Hyoungbae, Lim, Dong-Hyuk, Kang, Gunil, Park, Sang-Hune, Meghelli, Mounir, Rhew, Hyo-Gyuem, Friedman, Daniel, Choi, Michael, Soyuer, Mehmet, Shin, Jongshin

“…A 56 GS/s 8-bit asynchronous SAR ADC fabricated in 4nm CMOS technology is demonstrated. The 16x4 interleaved ADC uses a novel bootstrapping technique and a…”
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A 1.8 pJ/bit 16 \times 16\;\text Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration by Dickson, Timothy O., Liu, Yong, Agrawal, Ankur, Bulzacchelli, John F., Ainspan, Herschel A., Toprak-Deniz, Zeynep, Parker, Benjamin D., Beakes, Michael P., Meghelli, Mounir, Friedman, Daniel J.

“…A source-synchronous I/O architecture is reported that includes redundant receiver lanes to enable lane recalibration with reduced power and area overhead. Key…”
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A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology by Gangasani, G. R., Chun-Ming Hsu, Bulzacchelli, J. F., Rylov, S., Beukema, T., Freitas, D., Kelly, W., Shannon, M., Jieming Qi, Xu, H. H., Natonio, J., Rasmus, T., Jong-Ru Guo, Wielgos, M., Garlett, J., Sorna, M. A., Meghelli, M.

“…This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for…”
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