Search Results - "Buchwalter, L.P."

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias by Knickerbocker, J.U., Patel, C.S., Andry, P.S., Tsang, C.K., Buchwalter, L.P., Sprogis, E.J., Hua Gan, Horton, R.R., Polastre, R.J., Wright, S.L., Cotte, J.M.

“…System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage…”
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Tantalum, tantalum nitride, and chromium adhesion to polyimide: effect of annealing ambient on adhesion by Buchwalter, L.P., Holloway, K.

“…The adhesion of Ta, TaN (cubic), TaN x (mixture of cubic and amorphous phases), and Cr to 3,3',4,4'-biphenylene tetracarboxylic acid…”
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Characterization of micro-bump C4 interconnects for Si-carrier SOP applications by Wright, S.L., Polastre, R., Gan, H., Buchwalter, L.P., Horton, R., Andry, P.S., Sprogis, E., Patel, C., Tsang, C., Knickerbocker, J., Lloyd, J.R., Sharma, A., Sri-Jayantha, M.S.

“…This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and…”
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Reaction of polyaniline with NMP at elevated temperatures by Afzali, A., Buchwalter, S.L., Buchwalter, L.P., Hougham, G.

“…Heating a dilute solution of polyaniline emeraldine base in 1-methyl-2 pyrrolidinone under nitrogen at elevated temperatures resulted in the reduction of PANI…”
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A CMOS-compatible process for fabricating electrical through-vias in silicon by Andry, P.S., Tsang, C., Sprogis, E., Patel, C., Wright, S.L., Webb, B.C., Buchwalter, L.P., Manzer, D., Horton, R., Polastre, R., Knickerbocker, J.

“…In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming…”
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Poly(methyl methacrylate) degradation during x‐ray photoelectron spectroscopy analysis by Buchwalter, L. P., Czornyj, G.

“…Poly(methyl methacrylate) (PMMA) was chosen as a model lithographic material to study the effect of A1 K α radiation and the thermal (flood gun) electron flux…”
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System-on-package (SOP) technology, characterization and applications by Knickerbocker, J.U., Andry, P.S., Buchwalter, L.P., Colgan, E.G., Cotte, J., Gan, H., Horton, R.R., Sri-Jayantha, S.M., Magerlein, J.H., Manzer, D., McVicker, G., Patel, C.S., Polastre, R.J., Sprogis, E.S., Tsang, C.K., Webb, B.C., Wright, S.L.

“…A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance…”
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Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver by Patel, C.S., Tsang, C.K., Schuster, C., Doany, F.E., Nyikal, H., Baks, C.W., Budd, R., Buchwalter, L.P., Andry, P.S., Canaperi, D.F., Edelstein, D.C., Horton, R., Knickerbocker, J.U., Krywanczyk, T., Kwark, Y.H., Kwietniak, K.T., Magerlein, J.H., Rosner, J., Sprogis, E.

“…The design, fabrication, assembly and characterization of a novel silicon carrier package used for enabling a Tb/s parallel optical transceiver is reported…”
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Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization by Gan, H., Wright, S.L., Polastre, R., Buchwalter, L.P., Horton, R., Andry, P.S., Patel, C., Tsang, C., Knickerbocker, J., Sprogis, E., Pavlova, A., Kang, S.K., Lee, K.W.

“…To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a…”
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Simultaneous fabrication of RF MEMS switches and resonators using copper-based CMOS interconnect manufacturing methods by Jahnes, C.V., Cotte, J., Lund, J.L., Deligianni, H., Chinthakindi, A., Buchwalter, L.P., Fryer, P., Tornello, J.A., Hoivik, N., Magerlein, J.H., Seeger, D.

“…This paper describes the successful concurrent fabrication of micro-electro-mechanical (MEM) electrostatic switches and resonators on the same wafer. Base…”
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