Search Results - "Brunsilius, Janet"
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A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
Published in IEEE journal of solid-state circuits (01-12-2017)“…A 12-bit 10-GS/s interleaved (IL) pipeline analog-to-digital converter (ADC) is described in this paper. The ADC achieves a signal to noise and distortion…”
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Journal Article -
2
A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration
Published in IEEE journal of solid-state circuits (01-12-2014)“…We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and…”
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Journal Article -
3
16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology
Published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) (01-02-2017)“…Software defined radios and wideband instrumentation demand the ability to digitize wide BW RF signals with moderately high dynamic range. A 12b 10GS/s ADC…”
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Conference Proceeding -
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A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC
Published in 2011 IEEE International Solid-State Circuits Conference (01-02-2011)“…The high channel count of many modern communication systems increasingly requires high-performance ADCs that consume very little power. The 16b pipeline ADC…”
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Conference Proceeding -
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29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration
Published in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (01-02-2014)“…We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory…”
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Conference Proceeding