Search Results - "Briday, Mikaël"

A Study in Specification and Hardware Runtime Verification of Critical Embedded Software by Solet, Dimitry, Bechennec, Jean-Luc, Briday, Mikael, Faucou, Sebastien, Pillement, Sebastien

“…We evaluate HARVEST (Hardware Accelerated Runtime Verification for Embedded SofTware), a runtime error detection mechanism for embedded software running on…”
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Design and verification of pipelined circuits with Timed Petri Nets by Parrot, Rémi, Briday, Mikaël, Roux, Olivier H.

“…A fundamental step in circuit design is the placement of pipeline stages, which can drastically increase the data throughput. Retiming allows optimizing the…”
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SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems by Reymond, Hugo, Bechennec, Jean-Luc, Briday, Mikael, Faucou, Sebastien, Puaut, Isabelle, Rohou, Erven

“…Battery-free devices enable sensing in hard-to-access locations, opening up new opportunities in various fields such as healthcare, space, or civil…”
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Pipeline Optimization using a Cost Extension of Timed Petri Nets by Parrot, Remi, Briday, Mikael, Roux, Olivier H.

“…A major step in arithmetic operators design is the placement of pipeline stages, with the goal of drastically increase the data throughput. Approaches, such as…”
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EarlyBird: Energy belongs to those who wake up early by Reymond, Hugo, Bechennec, Jean-Luc, Briday, Mikael, Faucou, Sebastien, Puaut, Isabelle, Rohou, Erven

“…By relying on ambient energy, battery-less devices significantly increase the autonomy of IoT devices, enabling maintenance-free operation in remote locations…”
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Device driver synthesis for embedded systems by Tanguy, Julien, Bechennec, Jean-Luc, Briday, Mikael, Dube, Sebastien, Roux, Olivier H.

“…Currently the development of embedded software managing hardware devices that fulfills industrial constraints (safety, real time constraints) is a very complex…”
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Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems by Bernabeu, Antoine, Béchennec, Jean-Luc, Briday, Mikael, Faucou, Sebastien, Roux, Olivier

“…Intermittent computing is an emerging paradigm for systems without batteries and powered by intermittent energy sources. This paradigm promises a more…”
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HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems by Solet, Dimitry, Pillement, Sebastien, Bechennec, Jean-Luc, Briday, Mikael, Faucou, Sebastien

“…Runtime verification provides a theoretical proved framework to synthesize monitors from formal specifications. At runtime, these monitors can be used to check…”
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Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection by Solet, Dimitry, Bechennec, Jean-Luc, Briday, Mikael, Faucou, Sebastien, Pillement, Sebastien

“…Nowadays complete systems can be built on a System-on-a-Programmable-Chip that integrates a microcontroller and a FPGA fabric into a single chip. Beside its…”
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Harmless, a hardware architecture description language dedicated to real-time embedded system simulation by Kassem, Rola, Briday, Mikaël, Béchennec, Jean-Luc, Savaton, Guillaume, Trinquet, Yvon

“…Validation and verification of embedded systems through simulation can be conducted at many levels, from the simulation of a high-level application model to…”
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Reactive embedded device driver synthesis using logical timed models by Tanguy, Julien, Bechennec, Jean-Luc, Briday, Mikael, Roux, Olivier-H

“…The critical nature of hard real-time embedded systems leads to an increased usage of Model Based Design to generate a correct-by-construction code from a…”
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Securing a RISC-V architecture: A dynamic approach by Pillement, S., Real, M. Mendez, Pottier, J., Nieddu, T., Gal, B. Le, Faucou, S., Bechennec, J.L., Briday, M., Girbal, S., Rhun, J. Le, Gilles, O., Perez, D. Gracia, Sintzoff, A., Coulon, J.R.

“…The SecureV (also known as SecV) project offers an innovative, open-source hardware, secure, and high-performance processor core based on the RISC-V ISA. The…”
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Simulator generation using an automaton based pipeline model for timing analysis by Kassem, R., Briday, M., Bechennec, J.-L., Trinquet, Y., Savaton, G.

“…Hardware simulation is an important part of the design of embedded and/or real-time systems. It can be used to compute the Worst Case Execution Time (WCET) and…”
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Hardware runtime verification of embedded software in SoPC by Solet, Dimitry, Bechennec, Jean-Luc, Briday, Mikaol, Faucou, Sebastien, Pillement, Sebastien

“…This paper discusses an implementation of runtime verification for embedded software running on a System-on-Programmable-Chip (SoPC) composed of a…”
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Extending Harmless architecture description language for embedded real-time systems validation by Bechennec, J.-L, Briday, M., Alibert, V.

“…Harmless is a hardware architecture description language targeted to the simulation of embedded and realtime software. It allows to describe the instruction…”
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ReTiS: a real-time simulation tool for the analysis of distributed real-time applications by Briday, M., Bechennec, J.-L., Trinquet, Y.

“…This paper presents a simulation tool for real-time applications analysis. Simulation concerns the operational architecture and takes into account the…”
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Task scheduling observation and stack safety analysis in real time distributed systems using a simulation tool by Briday, M., Bechennec, J.-L., Trinquet, Y.

“…This paper presents the ReTiS simulation tool and its use for real-time application analysis. Simulation concerns the operational architecture and takes into…”
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