Search Results - "Bresson, N."

Integration of buried insulators with high thermal conductivity in SOI MOSFETs: Thermal properties and short channel effects by Bresson, N., Cristoloveanu, S., Mazuré, C., Letertre, F., Iwai, H.

“…SOI circuits exhibit excellent performance and scalability but suffer from self-heating. Systematical 2D simulations demonstrate that the thermal dissipation…”
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Electron magnetoresistance mobility in silicon-on-insulator layers using Kelvin’s technique by Antoszewski, J., Dell, J.M., Faraone, L., Bresson, N., Cristoloveanu, S.

“…The electron mobility in silicon-on-insulator (SOI) layers has been extracted from magnetoresistance data measured on a four concentric ring test structure,…”
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Possible influence of the Schottky contacts on the characteristics of ultrathin SOI pseudo-MOS transistors by Sato, S., Komiya, K., Bresson, N., Omura, Y., Cristoloveanu, S.

“…The paper describes the impact of pseudo-MOS technique on threshold and flatband voltages, and why the threshold and flatband voltages depend on…”
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Innovating SOI films: impact of thickness and temperature by Bresson, N, Cristoloveanu, S

“…Novel Unibond wafers, with very thin film and buried oxide, are probed with the pseudo-MOSFET method. It is shown that the method is still efficient at high…”
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Detailed investigation of geometrical factor for pseudo-MOS transistor technique by Komiya, K., Bresson, N., Shingo Sato, Cristoloveanu, S., Omura, Y.

“…The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and…”
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Characterization of multiple Si∕SiO2 interfaces in silicon-on-insulator materials via second-harmonic generation by Jun, B., White, Y. V., Schrimpf, R. D., Fleetwood, D. M., Brunier, F., Bresson, N., Cristoloveanu, S., Tolk, N. H.

“…Charge generation, transport, and recombination processes in UNIBOND® silicon-on-insulator wafers are studied via an optical second-harmonic generation (SHG)…”
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Through Silicon Via technology using tungsten metallization by Pares, G, Bresson, N, Minoret, S, Lapras, V, Brianceau, P, Lugand, J F, Anciant, R, Sillon, N

“…Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for…”
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Die to Wafer Direct Hybid Bonding Demonstration with High Alignment Accuracy and Electrical Yields by Jouve, A., Sanchez, L., Castan, C., Bresson, N., Fournel, F., Raynaud, N., Metzger, P.

“…Die-To-Wafer (D2W) direct hybrid bonding is foreseen as a major breakthrough for the future of 3D components; however, its industrialization rises some…”
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3D interconnection using copper direct hybrid bonding for GaN on silicon wafer by Dubarry, C., Arnaud, L., Munoz, M. L. Calvo, Mauguen, G., Moreau, S., Crochemore, R., Bresson, N., Aventurier, B.

“…3D integration of wafers stacking is obtained with a GaN-based wafer integrated on Si substrate and CMOS wafer. In this study, after planarization of the…”
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Charge trapping in irradiated SOI wafers measured by second harmonic generation by Bongim Jun, Schrimpf, R.D., Fleetwood, D.M., White, Y.V., Pasternak, R., Rashkeev, S.N., Brunier, F., Bresson, N., Fouillat, M., Cristoloveanu, S., Tolk, N.H.

“…Total dose effects on silicon on insulator (SOI) UNIBOND wafers are studied via optical second harmonic generation (SHG). This technique is qualitatively…”
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Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements by Gallon, C., Fenouillet-Beranger, C., Bresson, N., Cristoloveanu, S., Allibert, F., Bord, S., Aulnette, C., Delille, D., Latu-Romain, E., Hartmann, J.M., Ernst, T., Andrieu, F., Campidelli, Y., Ghyselen, B., Cayrefourcq, I., Fournel, F., Kernevez, N., Skotnicki, T.

“…Pseudo-MOS (Ψ -MOSFET) measurements are a simple and rapid technique for an accurate evaluation of SOI wafer intrinsic electrical properties, prior to any CMOS…”
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A simple test structure for the electrical characterization of front and back channels for advanced SOI technology development by Alepidis, M., Ionica, I., Milesi, F., Bresson, N., Gaudin, G., Cristoloveanu, S., Reboh, S.

“…•Double gate structures for channel material and gate stack characterization.•Easy and simple techniques based on the pseudo-MSOFET configuration.•Fast…”
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Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development by Bourjot, E., Stewart, P., Dubarry, C., Lagoutte, E., Rolland, E., Bresson, N., Romano, G., Scevola, D., Balan, V., Dechamp, J., Zussy, M., Mauguen, G., Castan, C., Sanchez, L., Jouve, A., Fournel, F., Cheramy, S.

“…Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches…”
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Electrical characterization of ultra-thin SOI films: comparison of the pseudo-MOSFET and Hg-FET techniques by Allibert, F., Bresson, N., Bellatreche, K., Maunand-Tussot, C., Cristoloveanu, S.

“…As the MOSFETs dimensions are scaled down, following the ITRS roadmap, the need for SOI wafers with ultra-thin Si films (UTF) becomes acute. Characterization…”
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Effects of stress in polysilicon VIA - first TSV technology by Parès, G, Bresson, N, Moreau, S, Lapras, V, Henry, D, Sillon, N

“…Through Silicon Via (TSV) is a very attractive solution for 3D stacking. One of the main concerns regarding the TSV technologies is the resulting stress build…”
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Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability by Arnaud, L., Moreau, S., Jouve, A., Jani, I., Lattard, D., Fournel, F., Euvrard, C., Exbrayat, Y., Balan, V., Bresson, N., Lhostis, S., Jourdon, J., Deloffre, E., Guillaumet, S., Farcy, A., Gousseau, S., Arnoux, M.

“…This paper presents the description of direct hybrid bonding technology for the fabrication of vertical interconnects thanks to wafer-to-wafer bonding. Process…”
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Effect of passivation annealing on the electromigration properties of hybrid bonding stack by Jourdon, J., Moreau, S., Bouchu, D., Lhostis, S., Bresson, N., Guiheux, D., Beneyton, R., Renard, S., Fremont, H.

“…This paper presents electromigration results on a hybrid bonding-based test vehicle to study the impact of bonding and passivation annealings on backend of…”
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Detailed investigation of geometrical factor for pseudo-MOS technique by Komiya N. Bresson S. Sato S. Cristoloveanu Y. Omura, K.

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Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness by Jourdon, J., Lhostis, S., Moreau, S., Chossat, J., Arnoux, M., Sart, C., Henrion, Y., Lamontagne, P., Arnaud, L., Bresson, N., Balan, V., Euvrard, C., Exbrayat, Y., Scevola, D., Deloffre, E., Mermoz, S., Martin, A., Bilgen, H., Andre, F., Charles, C., Bouchu, D., Farcy, A., Guillaumet, S., Jouve, A., Fremont, H., Cheramy, S.

“…Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A…”
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Alternative dielectrics for advanced SOI MOSFETs: thermal properties and short channel effects by Bresson, N., Cristoloveanu, S., Oshima, K., Mazure, C., Letertre, F., Iwai, H.

“…SOI devices exhibit excellent performance and scalability, but the presence of the buried oxide (BOX) induces self-heating. A possible solution is to replace…”
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