Search Results - "Brederlow, R."

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  1. 1

    Modeling of statistical low-frequency noise of deep-submicrometer MOSFETs by Wirth, G.I., Jeongwook Koh, da Silva, R., Thewes, R., Brederlow, R.

    Published in IEEE transactions on electron devices (01-07-2005)
    “…The low-frequency noise (LF-noise) of deep-submicrometer MOSFETs is experimentally studied with special emphasis on yield relevant parameter scattering. A…”
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    Journal Article
  2. 2

    Device and technology evolution for Si-based RF integrated circuits by Bennett, H.S., Brederlow, R., Costa, J.C., Cottrell, P.E., Huang, W.M., Immorlica, A.A., Mueller, J.-E., Racanelli, M., Shichijo, H., Weitzel, C.E., Bin Zhao

    Published in IEEE transactions on electron devices (01-07-2005)
    “…The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for…”
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    Journal Article
  3. 3

    Efficiency of body biasing in 90-nm CMOS for low-power digital circuits by von Arnim, K., Borinski, E., Seegebrecht, P., Fiedler, H., Brederlow, R., Thewes, R., Berthold, J., Pacha, C.

    Published in IEEE journal of solid-state circuits (01-07-2005)
    “…The efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated…”
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    Journal Article Conference Proceeding
  4. 4

    A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs by Jeongwook Koh, Schmitt-Landsiedel, D., Thewes, R., Brederlow, R.

    Published in IEEE journal of solid-state circuits (01-06-2007)
    “…We present a novel principle for 1/f noise reduction in linear analog CMOS ICs. The principle is experimentally demonstrated for a two-stage CMOS Miller…”
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    Journal Article
  5. 5

    Fully-integrated LDO voltage regulator for digital circuits by LÈ­ders, M, Eversmann, B, Schmitt-Landsiedel, D, Brederlow, R

    Published in Advances in radio science (01-08-2011)
    “…Low-dropout (LDO) voltage regulators are widely used to supply low-voltage digital circuits. For recent ultra-low-power microcontroller systems, a…”
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    Journal Article
  6. 6

    Hot-carrier degradation of the low-frequency noise in MOS transistors under analog and RF operating conditions by Brederlow, R., Weber, W., Schmitt-Landsiedel, D., Thewes, R.

    Published in IEEE transactions on electron devices (01-09-2002)
    “…We investigate the hot-carrier degradation of the 1/f-noise behavior of nand p-MOS transistors under typical bias conditions for analog and RF operation. The…”
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    Journal Article
  7. 7

    Low-frequency noise of integrated poly-silicon resistors by Brederlow, R, Weber, W, Dahl, C, Schmitt-Landsiedel, D, Thewes, R

    Published in IEEE transactions on electron devices (01-06-2001)
    “…This paper presents an analytical first principle model for the low-frequency noise current of poly-silicon layers used as resistors in analog CMOS…”
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    Journal Article
  8. 8
  9. 9

    An Ultra Low Power Bandgap Operational at Supply From 0.75 V by Ivanov, V., Brederlow, R., Gerber, J.

    Published in IEEE journal of solid-state circuits (01-07-2012)
    “…We present an ultra low power (200 nA current consumption) reverse bandgap voltage reference operational from supply voltages down to 0.75 V. The reference is…”
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    Journal Article Conference Proceeding
  10. 10

    On the design robustness of threshold logic gates using multi-input floating gate MOS transistors by Luck, A., Jung, S., Brederlow, R., Thewes, R., Goser, K., Weber, W.

    Published in IEEE transactions on electron devices (01-06-2000)
    “…In this paper, the design robustness of logic circuits implemented as threshold logic gates with multi-input floating gate transistors is analyzed. The…”
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    Journal Article
  11. 11

    A low-power true random number generator using random telegraph noise of single oxide-traps by Brederlow, R., Prakash, R., Paulus, C., Thewes, R.

    “…A true random number generator is realized by utilizing the noise produced by single oxide traps in small-area MOSFETs in combination with built-in redundancy…”
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    Conference Proceeding
  12. 12

    MOS transistor reliability under analog operation by Thewes, R., Brederlow, R., Schlunder, C., Wieczorek, P., Ankele, B., Hesener, A., Holz, J., Kessel, S., Weber, W.

    Published in Microelectronics and reliability (01-08-2000)
    “…Reliability evaluation for MOS transistors under analog operation requires different or specifically adapted approaches compared to the ones known from the…”
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    Journal Article
  13. 13

    On the degradation of p-MOSFETs in analog and RF circuits under inhomogeneous negative bias temperature stress by Schlunder, C., Brederlow, R., Ankele, B., Lill, A., Goser, K., Thewes, R.

    “…The effect of inhomogeneous Negative Bias Temperature Stress (NBTS) applied to p-MOS transistors under analog and RF CMOS operating conditions is investigated…”
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    Conference Proceeding
  14. 14

    Low-frequency noise of integrated polysilicon resistors by Brederlow, R., Weber, W., Dahl, C., Schmitt-Landsiedel, D., Thewes, R.

    Published in IEEE transactions on electron devices (01-06-2001)
    “…This paper presents an analytical first principle model for the low-frequency noise current of polysilicon layers used as resistors in analog CMOS…”
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    Journal Article
  15. 15

    AC-only RF ID tags for barcode replacement by Briole, S., Pacha, C., Goser, K., Kaiser, A., Thewes, R., Weber, W., Brederlow, R.

    “…An RF ID concept using ac-powered circuits without DC conversion is demonstrated for barcode replacement. A 32b codeword ID tag including an RF front-end,…”
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    Conference Proceeding
  16. 16

    A physics-based low frequency noise model for MOSFETs under periodic large signal excitation by Brederlow, R., Jeongwook Koh, Thewes, R.

    “…In recent years several publications have reported reductions in the low frequency noise of MOSFETs under large signal excitation presented in I. Bloom et al…”
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    Conference Proceeding
  17. 17

    An ultra-low power, 2mA Iout buck converter optimized for <50mV ripple at a load cap of only 27nF by Santoro, F., Schmitt-Landsiedel, D., Gibson, N., Kuhn, R., Tost, T., Brederlow, R.

    “…A novel, simple DC-DC concept for low-power applications is presented. We propose a predictive peak-current mode controller in discontinuous conduction mode…”
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    Conference Proceeding
  18. 18

    Mismatch of MOSFET small signal parameters under analog operation by Thewes, R., Linnenbank, C., Kollmer, U., Burges, S., Schaper, U., Brederlow, R., Weber, W.

    Published in IEEE electron device letters (01-12-2000)
    “…The matching behavior of drain current I/sub D/ and small signal parameters transconductance g/sub m/ and differential output conductance g/sub DS/ of MOSFETs…”
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    Journal Article
  19. 19

    A 128 × 128 CMOS biosensor array for extracellular recording of neural activity by Eversmann, B, Jenkner, M, Hofmann, F, Paulus, C, Brederlow, R, Holzapfl, B, Fromherz, P, Merz, M, Brenner, M, Schreiter, M, Gabl, R, Plehnert, K, Steinhauser, M, Eckstein, G, Schmitt-Landsiedel, D, Thewes, R

    Published in IEEE journal of solid-state circuits (01-12-2003)
    “…Sensor arrays are a key tool in the field of neuroscience for noninvasive recording of the activity of biological networks, such as dissociated neurons or…”
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    Journal Article
  20. 20

    CMOS-Based Biosensor Arrays by Thewes, R., Paulus, C., Schienle, M., Hofmann, F., Frey, A., Brederlow, R., Augustyniak, M., Jenkner, M., Eversmann, B., Schindler-Bauer, P., Atzesberger, M., Holzapfl, B., Beer, G., Haneder, T., Hanke, H.-C.

    Published in Design, Automation and Test in Europe (07-03-2005)
    “…CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications…”
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    Conference Proceeding