Scaling NbTiN-based ac-powered Josephson digital to 400M devices/cm$^2
We describe a fabrication stackup for digital logic with 16 superconducting NbTiN layers, self-shunted a-silicon barrier Josephson Junctions (JJs), and low loss, high-$\kappa$ tunable HZO capacitors. The stack enables 400 MJJ/cm$^2$ device density, efficient routing, and AC power distribution on a r...
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| Main Authors: | , , , , , , , , , , , |
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| Format: | Journal Article |
| Language: | English |
| Published: |
29-03-2023
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| Subjects: | |
| Online Access: | Get full text |
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| Summary: | We describe a fabrication stackup for digital logic with 16 superconducting
NbTiN layers, self-shunted a-silicon barrier Josephson Junctions (JJs), and low
loss, high-$\kappa$ tunable HZO capacitors. The stack enables 400 MJJ/cm$^2$
device density, efficient routing, and AC power distribution on a resonant
network. The materials scale beyond 28nm lithography and are compatible with
standard high-temperature CMOS processes. We report initial results for
two-metal layer NbTiN wires with 50nm critical dimension. A semi-ascendance
wire-and-via process module using 193i lithography and 50nm critical dimension
has shown cross-section uniformity of 1%=1s across the 300mm wafer, critical
temperature of 12.5K, and critical current of 0.1mA at 4.2K. We also present a
new design of the resonant AC power network enabled by NbTiN wires and HZO MIM
capacitors. The design matches the device density and provides a 30 GHz clock
with estimated efficiency of up to 90%. Finally, magnetic imaging of patterned
NbTiN ground planes shows low intrinsic defectivity and consistent trapping of
vorteces in 0.5 mm holes spaced on a 20 $\mu$m x 20 $\mu$m grid. |
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| DOI: | 10.48550/arxiv.2303.16792 |