Search Results - "Braendli, M."

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    A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS by Cevrero, A., Aprile, C., Francese, P. A., Bapst, U., Menolfi, C., Braendli, M., Kossel, M., Morf, T., Kull, L., Yueksel, H., Oezkaya, I., Leblebici, Y., Cevher, V., Toifl, T.

    “…This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a…”
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    Conference Proceeding Journal Article
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    Room-temperature THz imaging based on antenna-coupled MOSFET bolometer by Morf, T., Klein, B., Despont, M., Drechsler, U., Kull, L., Corcos, D., Elad, D., Kaminski, N., Braendli, M., Menolfi, C., Kossel, M., Francese, P. A., Toifl, T., Plettemeier, D.

    “…We report on the design, fabrication and measurements of a new THz sensor concept based on an antenna-coupled MOSFET bolometer for room-temperature passive THz…”
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    Conference Proceeding Journal Article
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    A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS by Kull, L., Toifl, T., Schmatz, M., Francese, P. A., Menolfi, C., Braendli, M., Kossel, M., Morf, T., Andersen, T. M., Leblebici, Y.

    “…Next-generation digital high-speed links require fast, yet energy-efficient ADCs at minimum area. Recent years saw impressive progress in SAR ADC designs…”
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    Conference Proceeding
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    A 28Gb/s source-series terminated TX in 32nm CMOS SOI by Menolfi, C., Hertle, J., Toifl, T., Morf, T., Gardellini, D., Braendli, M., Buchmann, P., Kossel, M.

    “…Upcoming standards such as OIF CEI-25LR and CEI-28SR demand transmitter circuits above 20Gb/s [1]-[3] with stringent jitter requirements. The SST driver…”
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    Conference Proceeding
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    A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI by Menolfi, C, Toifl, T, Rueegg, M, Braendli, M, Buchmann, P, Kossel, M, Morf, T

    “…The limited supply voltage of today's state-of-the-art CMOS technologies makes the design of high-speed transmitters at signaling swings above the typical 1 V…”
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    Conference Proceeding
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    A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS by Toifl, T., Menolfi, C., Braendli, M., Cevrero, A., Francese, P. A., Kossel, M., Kull, L., Luu, D., Morf, T., Ozkaya, I.

    Published in 2018 IEEE Symposium on VLSI Circuits (01-06-2018)
    “…We present a digital implementation of a TX precoder/ equalizer that, similar to a Tomlinson-Harashima Precoder (THP), provides a decision feedback equalizer…”
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    Conference Proceeding
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    A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET by Cevrero, A., Ozkaya, I., Francese, P. A., Menolfi, C., Braendli, M., Morf, T., Kuchta, D., Kossel, M., Kull, L., Luu, D., Proesel, J., Leblebici, Y., Toifl, T.

    Published in 2017 Symposium on VLSI Circuits (01-06-2017)
    “…This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high…”
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    Conference Proceeding
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    Design of a wide-bandwidth on-chip antenna for uncooled passive THz imaging by Klein, B., Morf, T., Despont, M., Drechsler, U., Corcos, D., Kaminski, N., Elad, D., Kull, L., Braendli, M., Toifl, T., Hahnel, R., Plettemeier, D.

    “…The design of a broadband on-chip antenna for passive THz imaging in the frequency range of 0.6 THz to 1.4 THz is reported. The antenna design has to fulfill…”
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    Conference Proceeding
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