Search Results - "Boyd, D.C."

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics by Min Yang, Gusev, E.P., Meikei Ieong, Gluschenkov, O., Boyd, D.C., Chan, K.K., Kozlowski, P.M., D'Emic, C.P., Sicina, R.M., Jamison, P.C., Chou, A.I.

“…Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness…”
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A high-speed, high-sensitivity silicon lateral trench photodetector by Min Yang, Kern Rim, Rogers, D.L., Schaub, J.D., Welser, J.J., Kuchta, D.M., Boyd, D.C., Rodier, F., Rabidoux, P.A., Marsh, J.T., Ticknor, A.D., Qingyun Yang, Upham, A., Ramac, S.C.

“…We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed…”
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Two gates are better than one [double-gate MOSFET process] by Solomon, P.M., Hovel, H.J., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K., Yoon, J.H., Babich, I.V., Treichler, J., Guarini, K.W., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Benedict, J., Wong, H.-S.P., Zhang, Y., Chan, K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O.

“…A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of…”
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N-channel MOSFETs fabricated on He-implanted and annealed SiGe buffer layers by Mooney, P.M., Rim, K., Christiansen, S.H., Chan, K.K., Chu, J.O., Cai, J., Chen, H., Jordan-Sweet, J.L., Yang, Y.Y., Boyd, D.C.

“…He-implantation and annealing is an alternative method of fabricating strain-relaxed SiGe buffer layers for applications such as strained Si MOSFETs. Here we…”
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Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO 2 gate dielectrics by Min Yang, Gusev, E.P., Meikei Ieong, Gluschenkov, O., Boyd, D.C., Chan, K.K., Kozlowski, P.M., D'Emic, C.P., Sicina, R.M., Jamison, P.C., Chou, A.I.

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On the integration of CMOS with hybrid crystal orientations by Yang, M., Chan, V., Ku, S.H., Ieong, M., Shi, L., Chan, K.K., Murthy, C.S., Mo, R.T., Yang, H.S., Lehner, E.A., Surpris, Y., Jamin, F.F., Oldiges, P., Zhang, Y., To, B.N., Holt, J.R., Steen, S.E., Chudzik, M.P., Fried, D.M., Bernstein, K., Zhu, H., Sung, C.Y., Ott, J.A., Boyd, D.C., Rovedo, N.

“…Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring…”
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Familial aggregation of memory and attentional deficits in schizophrenia by Moldin, S.O., Newcomer, J.W., Richter, J.S., Boyd, D.C.

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Triple-self-aligned, planar double-gate MOSFETs: devices and circuits by Guarini, K.W., Solomon, P.M., Zhang, Y., Chan, K.K., Jones, E.C., Cohen, G.M., Krasnoperova, A., Ronay, M., Dokumaci, O., Bucchignano, J.J., Cabral, C., Lavoie, C., Ku, V., Boyd, D.C., Petrarca, K.S., Babich, I.V., Treichler, J., Kozlowski, P.M., Newbury, J.S., D'Emic, C.P., Sicina, R.M., Wong, H.-S.

“…We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed…”
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Integration of 10 Gb/sec silicon lateral trench photodetector with high-performance CMOS by Yang, M., Schaub, J.D., Rogers, D.L., Griesemer, J.A., Boyd, D.C., Zhang, B., Rodier, F., Flaitz, P.L., McMurray, J.S., Chan, K.K., Kim, B., Breitwisch, M.J., Walko, J.P., Pendleton, D., Holloway, K.L., Ritter, M.B., Kash, J.A., Leong, M.

“…In this paper,we demonstrate the integration of optimized LTDs with 0.13/spl mu/m CMOS technology. Excellent characteristics were achieved for both the…”
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Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication by Guarini, K.W., Topol, A.W., Ieong, M., Yu, R., Shi, L., Newport, M.R., Frank, D.J., Singh, D.V., Cohen, G.M., Nitta, S.V., Boyd, D.C., O'Neil, P.A., Tempest, S.L., Pogge, H.B., Purushothaman, S., Haensch, W.E.

“…We introduce a new scheme for building three-dimensional (3D) integrated circuits (ICs) based on the layer transfer of completed devices. We demonstrate for…”
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A review of the methods of automatic analysis in clinical electromyography by Boyd, D C, Bratty, P J, Lawrence, P D

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