Search Results - "Both, Thiago H."

Random Telegraph Noise Modeling for Circuit Analysis: RTN in Ring Oscillators by da Silva, Mauricio Banaszeski, Both, Thiago H., Wirth, Gilson I.

“…In highly scaled MOSFETs, random telegraph noise (RTN) can decrease the reliability and yield of circuits. RTN is produced by charge trapping, which in large…”
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A Compact Statistical Model for the Low-Frequency Noise in Halo-Implanted MOSFETs: Large RTN Induced by Halo Implants by Banaszeski da Silva, Mauricio, Both, Thiago H., Tuinhout, Hans P., Zegers-van Duijnhoven, Adrie, Wirth, Gilson I., Scholten, Andries J.

“…In this paper, we propose a novel compact statistical model for the low-frequency noise (LFN) of MOS devices with halo implants. The compact model is suited…”
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Statistical analysis of the impact of charge traps in p-type MOSFETs via particle-based Monte Carlo device simulations by Rossetto, Alan C. J., Camargo, Vinicius V. A., Both, Thiago H., Vasileska, Dragica, Wirth, Gilson I.

“…In this paper, statistical analysis of the static impact of charge traps on the drain current of p -type metal–oxide–semiconductor field-effect transistors is…”
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Autocorrelation Analysis as a Technique to Study Physical Mechanisms of MOSFET Low-Frequency Noise by Both, Thiago H., Croon, Jeroen A., Banaszeski da Silva, Mauricio, Tuinhout, Hans P., Scholten, Andries J., Zegers-van Duijnhoven, Adrie, Wirth, Gilson I.

“…A low-frequency noise (LFN) analysis technique is introduced, based on the autocorrelation of the LFN spectra in terms of frequency, biasing, and temperature…”
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Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies by Kessler, Henrique, Finkenauer, Plinio, Both, Thiago H., da Rosa, Leomar, Camargo, Vinicius V.

“…This paper presents a study comparing complex gates that use Series-Parallel and Non-Series-Parallel associations, including the time-zero variability and the…”
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1/f noise simulation in MOSFETs under cyclo-stationary conditions using SPICE simulator by Both, Thiago H., Wirth, Gilson I., Vasileska, Dragica

“…The purpose of this work is to propose a methodology to compute 1/f noise in MOS transistors under cyclo-stationary operation using the standard BSIM4 noise…”
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An Analytical Gate Delay Variability Model for Low-Power and Low-Voltage Applications by Garcia, Caroline P., Both, Thiago H.

“…Understanding the timing characteristics behavior, such as the logic gate delay, is an essential task in ICs. In low-power and low-voltage devices, due to…”
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Towards Unifying the Statistical Modeling of Charge Trapping in Time and Frequency Domain by Wirth, Gilson, da Silva, Mauricio B., Both, Thiago H.

“…We discuss how charge trapping produces random telegraph noise (RTN) and low-frequency noise (1/f noise), working towards unified statistical modeling and…”
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Gate Delay Variability due to Random Telegraph Noise by Barbosa, Rodolfo G., Both, Thiago H., Wirth, Gilson

“…Stochastic timing variations are a major concern in nanometric CMOS logic gates. Addressing the time-zero fluctuations due to variability of physical…”
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Unified Compact Modeling of Charge Trapping in 1/f Noise, RTN and BTI by Wirth, Gilson, da Silva, Mauricio B., Both, Thiago H.

“…We review and critically discuss the unified statistical modeling of charge trapping in the context of 1/f noise, RTN and BTI. The focus is on circuit…”
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A variability-based analysis technique revealing physical mechanisms of MOSFET low-frequency noise by Both, Thiago H., Croon, Jeroen A., Banaszeski da Silva, Mauricio, Tuinhout, Hans P., Zegers-van Duijnhoven, Adrie, Scholten, Andries J., Wirth, Gilson I.

“…This paper presents a technique for statistical analysis of MOSFET low-frequency noise (LFN) based on the autocorrelation coefficient of numerous LFN power…”
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TID effects on I–V characteristics of bulk CMOS STD and ELT-based devices in 600 nm by Vaz, Pablo I., Wirth, Gilson I., Vidor, Fábio F., Both, Thiago H.

“…This work presents the Total Ionizing Dose (TID) effects on the I–V characteristics of multiple standard (STD) and enclosed-layout (ELT) bulk CMOS transistors…”
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Deterministic methodology to evaluate BTI impact on logic gates propagation delay by Furtado, Gabriela F., Both, Thiago H., Wirth, Gilson I.

“…The propagation delay variation induced by BTI in logic gates is studied. Using the deterministic BTI model introduced by our group in [1], a detailed…”
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Deterministic Methodology for Electrical Simulation of BTI Induced Pulse Broadening by Firpo Furtado, Gabriela, Both, Thiago H., Vieira, Michele, Wirth, Gilson I.

“…This paper presents an analysis of the bias temperature instability (BTI) induced pulse broadening of single event transients (SETs) in inverter chains. A…”
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