Search Results - "Bor-Wen Chan"

Synthesis and properties of thio-containing poly(ether ether ketone)s by Wang, Yen-Zen, Lin, Chih-Hung, Chan, Bor-Wen, Hsieh, Kuo-Huang

“…A series of thio‐containing poly(ether ether ketone) (PEESK) polymers was synthesized by the introduction of thio groups from 4,4′ thiodiphenol (TDP) into the…”
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Plasma induced substrate damage in high dose implant resist strip process by Bor-Wen Chan, Baw-Ching Perng, Sheu, L., Yuan-Hung Chiu, Han-Jan Tao

“…In this communication we report our work on the ashing of post high dosage implant photoresist removal. Attention is focused on plasma damage to the silicon…”
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Notch elimination in polycide gate stack etching for advanced DRAM technology by Bor-Wen Chan, Min-hwa Chi, Liou, Y.H.

“…The notch phenomenon in etching of complex TEOS/oxynitride/WSi/sub x//poly DRAM gate stacks is eliminated by adding N/sub 2/ gas in the poly over-etch (OE)…”
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5nm-gate nanowire FinFET by Fu-Liang Yang, Di-Hong Lee, Hou-Yu Chen, Chang-Yun Chang, Sheng-Da Liu, Cheng-Chuan Huang, Tang-Xuan Chung, Hung-Wei Chen, Chien-Chao Huang, Yi-Hsuan Liu, Chung-Cheng Wu, Chi-Chun Chen, Shih-Chang Chen, Ying-Tsung Chen, Ying-Ho Chen, Chih-Jian Chen, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Horng Shieh, Han-Jan Tao, Yee-Chia Yeo, Yiming Li, Jam-Wem Lee, Pu Chen, Mong-Song Liang, Chenming Hu

“…A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and…”
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Elimination of notch during gate polycide stack etching by adding nitrogen in over etch step by Bor-Wen Chan, Liou, Y.H., Min-Hwa Chi

“…In this paper, the notch phenomenon in sub-quarter-micron DRAM polycide gate etching process is an important issue and is improved by adding N/sub 2/ gas in…”
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5nm-Gate nanowire FinFET by YANG, Fu-Liang, LEE, Di-Hong, WU, Chung-Cheng, CHEN, Chi-Chun, CHEN, Shih-Chang, CHEN, Ying-Tsung, CHEN, Ying-Ho, CHEN, Chih-Jian, CHAN, Bor-Wen, HSU, Peng-Fu, SHIEH, Jyu-Homg, TAO, Han-Jan, CHEN, Hou-Yu, YEO, Yee-Chia, YIMING LI, LEE, Jam-Wem, PU CHEN, LIANG, Mong-Song, CHENMING HU, CHANG, Chang-Yun, LIU, Sheng-Da, HUANG, Cheng-Chuan, CHUNG, Tang-Xuan, CHEN, Hung-Wei, HUANG, Chien-Chao, LIU, Yi-Hsuan

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45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell by YANG, Fu-Liang, HUANG, Cheng-Chuan, WEN, Cheng-Kuo, CHENG, Shui-Ming, YANG, Chang-Ta, KUNG, Li-Wei, LEE, Chiu-Lien, CHOU, Yu-Jun, LIANG, Fu-Jye, SHIU, Lin-Hung, YOU, Jan-Wen, SHU, King-Chang, HUANG, Chien-Chao, CHANG, Bin-Chang, SHIN, Jaw-Jung, CHEN, Chun-Kuang, GAU, Tsai-Sheng, WANG, Ping-Wei, CHAN, Bor-Wen, HSU, Peng-Fu, SHIEH, Jyu-Horng, FUNG, Samuel K.-H, DIAZ, Carlos H, CHUNG, Tang-Xuan, WU, Chii-Ming M, SEE, Yee-Chaung, LIN, Burn J, LIANG, Mong-Song, SUN, Jack Y.-C, CHENMING HU, CHEN, Hou-Yu, CHANG, Chang-Yun, CHEN, Hung-Wei, LEE, Di-Hong, LIU, Sheng-Da, CHEN, Kuang-Hsin

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45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell by Fu-Liang Yang, Cheng-Chuan Huang, Chien-Chao Huang, Tang-Xuan Chung, Hou-Yu Chen, Chang-Yun Chang, Hung-Wei Chen, Di-Hong Lee, Sheng-Da Liu, Kuang-Hsin Chen, Cheng-Kuo Wen, Shui-Ming Cheng, Chang-Ta Yang, Li-Wei Kung, Chiu-Lien Lee, Yu-Jun Chou, Fu-Jye Liang, Lin-Hung Shiu, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Ping-Wei Wang, Bor-Wen Chan, Peng-Fu Hsu, Jyu-Honig Shieh, Fung, S.K.-H., Diaz, C.H., Wu, C.-M.M., Yee-Chaung See, Lin, B.J., Liang, M.-S., Sun, J.Y.-C., Chenming Hu

“…The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained…”
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A 65nm node strained SOI technology with slim spacer by Fu-Liang Yang, Chien-Chao Huang, Hou-Yu Chen, Jhon-Jhy Liaw, Tang-Xuan Chung, Hung-Wei Chen, Chang-Yun Chang, Cheng Chuan Huang, Kuang-Hsin Chen, Di-Hong Lee, Hsun-Chih Tsao, Cheng-Kuo Wen, Shui-Ming Cheng, Yi-Ming Sheu, Ke-Wei Su, Chi-Chun Chen, Tze-Liang Lee, Shih-Chang Chen, Chih-Jian Chen, Cheng-hung Chang, Jhi-cheng Lu, Weng Chang, Chuan-Ping Hou, Ying-Ho Chen, Kuei-Shun Chen, Ming Lu, Li-Wei Kung, Yu-Jun Chou, Fu-Jye Liang, Jan-Wen You, King-Chang Shu, Bin-Chang Chang, Jaw-Jung Shin, Chun-Kuang Chen, Tsai-Sheng Gau, Bor-Wen Chan, Yi-Chun Huang, Han-Jan Tao, Jyh-Huei Chen, Yung-Shun Chen, Yee-Chia Yeo, Fung, S.K.-H., Diaz, C.H., Wu, C.-M.M., Lin, B.J., Liang, M.-S., Sun, J.Y.-C., Chenming Hu

“…A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET,…”
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