High bandwidth low power interposer interconnect challenge, design, and validation in 3D silicon stacked interconnect (SSI) technology

This paper describes the characteristics of interposer interconnects in 3D silicon stacked interconnect (SSI) technology in comparison to traditional silicon interconnects. It explores unique near end crosstalk (NEXT) and far end crosstalk (FEXT) behavior of simple interposer interconnect structure...

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Bibliographic Details
Published in:	2016 IEEE International Symposium on Electromagnetic Compatibility (EMC) pp. 434 - 439
Main Authors:	Wong, Anna, Tsui, Gordon, Boon-Kai Soo, Chong-Ling Khoo, Yong Wang
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-07-2016
Subjects:	3D IC crosstalk Decision support systems Erbium interconnect interposer jitter Silicon Stacked Interconnect (SSI)) technology simultaneous switching noise (SSN)
Online Access:	Get full text
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Summary:	This paper describes the characteristics of interposer interconnects in 3D silicon stacked interconnect (SSI) technology in comparison to traditional silicon interconnects. It explores unique near end crosstalk (NEXT) and far end crosstalk (FEXT) behavior of simple interposer interconnect structure with simulation results. Six different routing structures were investigated for I/O density and signal integrity trade-off with emphasis in timing impact due to crosstalk. Analysis shows that the four routing structures with lower I/O density meet timing requirement set for 625MHz, whereas the remaining two routing structures with higher I/O density fail. The routing structure that demonstrates the best trade-off was implemented in a SSI technology test chip. Lab data shows that the timing impact from simultaneous switching noise (SSN) is less than 20% of timing budget at 625MHz targeted operating frequency.
ISSN:	2158-1118
DOI:	10.1109/ISEMC.2016.7571687