Search Results - "Boneti, C."

  • Showing 1 - 9 results of 9
Refine Results
  1. 1

    SMT Malleability in IBM POWER5 and POWER6 Processors by Morari, A., Boneti, C., Cazorla, F. J., Gioiosa, R., Chen-Yong Cher, Buyuktosunoglu, A., Bose, P., Valero, M.

    Published in IEEE transactions on computers (01-04-2013)
    “…While several hardware mechanisms have been proposed to control the interaction between hardware threads in an SMT processor, few have addressed the issue of…”
    Get full text
    Journal Article
  2. 2
  3. 3

    Axillary reverse mapping (ARM): initial results of phase II trial in preventing lymphedema after lymphadenectomy by Boneti, C, Badgwell, B, Robertson, Y, Korourian, S, Adkins, L, Klimberg, V

    Published in Minerva ginecologica (01-10-2012)
    “…Axillary reverse mapping (ARM) is unproven in preventing lymphedema. The purpose of this study is to evaluate lymphedema rates with ARM added to…”
    Get more information
    Journal Article
  4. 4
  5. 5

    Characterizing Power and Temperature Behavior of POWER6-Based System by Jimenez, V., Cazorla, F. J., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Chen-Yong Cher, Isci, C., Buyuktosunoglu, A., Bose, P.

    “…Microprocessor architectures have become increasingly power limited in recent years. Currently power and thermal envelopes dictate peak performance limits more…”
    Get full text
    Journal Article
  6. 6

    Software-Controlled Priority Characterization of POWER5 Processor by Boneti, Carlos, Cazorla, Francisco J., Gioiosa, Roberto, Buyuktosunoglu, Alper, Cher, Chen-Yong, Valero, Mateo

    “…Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the…”
    Get full text
    Conference Proceeding Publication
  7. 7

    A dynamic scheduler for balancing HPC applications by Boneti, C., Gioiosa, R., Cazorla, F.J., Valero, M.

    “…Load imbalance cause significant performance degradation in High Performance Computing applications. In our previous work we showed that load imbalance can be…”
    Get full text
    Conference Proceeding Publication
  8. 8

    Balancing HPC applications through smart allocation of resources in MT processors by Boneti, C., Gioiosa, R., Cazorla, F.J., Corbalan, J., Labarta, J., Valero, M.

    “…Many studies have shown that load imbalancing causes significant performance degradation in high performance computing (HPC) applications. Nowadays,…”
    Get full text
    Conference Proceeding
  9. 9