Search Results - "Black, Dolores"

The Effects of Gamma Ray Integrated Dose on a Commercial 65-nm SRAM Device by Stirk, Wesley, Black, Dolores A., Black, Jeffrey D., Breeding, Matthew, Cuoco, Roy P., Wirthlin, Mike, Goeders, Jeffrey

“…This work shows that the static random access memory (SRAM) error rate for a commercial 65-nm device in a dose rate environment can be highly dependent upon…”
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Modeling of Single Event Transients With Dual Double-Exponential Current Sources: Implications for Logic Cell Characterization by Black, Dolores A., Robinson, William H., Wilcox, Ian Z., Limbrick, Daniel B., Black, Jeffrey D.

“…Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage…”
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Impact of Surface Recombination on Single-Event Charge Collection in an SOI Technology by Tonigan, Andrew M., Ball, Dennis, Vizkelethy, Gyorgy, Black, Jeffrey, Black, Dolores, Trippe, James, Bielejec, Edward, Alles, Michael L., Reed, Robert, Schrimpf, Ronald D.

“…Semiconductor-insulator interfaces play an important role in the reliability of integrated devices; however, the impact of these interfaces on the physical…”
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Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Containing Boron-10 by Auden, Elizabeth C., Quinn, Heather M., Wender, Stephen A., O'Donnell, John M., Lisowski, Paul W., George, Jeffrey S., Xu, Ning, Black, Dolores A., Black, Jeffrey D.

“…Single-event upsets (SEUs) were measured in thermal neutron-irradiated microcontrollers with 65- and 130-nm-node static random-access memories (SRAMs). The…”
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Using MRED to Screen Multiple-Node Charge-Collection Mitigated SOI Layouts by Black, Jeffrey D., Dame, Jeff A., Black, Dolores A., Dodd, Paul E., Shaneyfelt, Marty R., Teifel, John, Salas, Joseph G., Steinbach, Robert, Davis, Matthew, Reed, Robert A., Weller, Robert A., Trippe, James M., Warren, Kevin M., Tonigan, Andrew M., Schrimpf, Ronald D., Marquez, Richard S.

“…Silicon-on-insulator latch designs and layouts that are robust to multiple-node charge collection are introduced. A general Monte Carlo radiative energy…”
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Understanding the Implications of a LINAC's Microstructure on Devices and Photocurrent Models by McLain, Michael L., McDonald, J. Kyle, Hembree, Charles E., Sheridan, Timothy J., Weingartner, Thomas A., Dodd, Paul E., Shaneyfelt, Marty R., Hartman, Fred, Black, Dolores A.

“…The effect of a linear accelerator's (LINAC's) microstructure (i.e., train of narrow pulses) on devices and the associated transient photocurrent models are…”
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DFF Layout Variations in CMOS SOI-Analysis of Hardening by Design Options by Black, Jeffrey D., Black, Dolores A., Domme, Nicholas A., Dodd, Paul E., Griffin, Patrick J., Nowlin, R. Nathan, Trippe, James M., Salas, Joseph G., Reed, Robert A., Weller, Robert A., Tonigan, Andrew M., Schrimpf, Ronald D

“…Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories' CMOS7 silicon-on-insulator (SOI) process. Single-event…”
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Impact of logic synthesis on soft error vulnerability using a 90-nm bulk CMOS digital cell library by Limbrick, Daniel B, Black, Dolores A, Dick, Kevin, Atkinson, Nicholas M, Gaspard, Nelson J, Black, Jeffrey D, Robinson, William H, Witulski, Arthur F

“…Reliability-aware logic synthesis can be used to mitigate a circuit's response to radiation-induced soft errors. This paper analyzes the impact of using…”
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Dynamic Testing of a Commercial FRAM Device Under Gamma Ray Dose and Neutron Beam by Harris, Nathan, Stirk, Wesley, Black, Dolores, Black, Jeffrey, Wirthlin, Mike, Goeders, Jeffrey

“…This work presents dose rate and neutron testing on a ferroelectric random-access memory (FRAM) device in dynamic operation during radiation pulses. Radiation…”
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Impact of ion-induced transients on high-speed dual-complementary Flip-Flop designs by Black, Dolores A, Reed, Robert A, Robinson, William H, Black, Jeffrey D, Limbrick, Daniel B, Dick, Kevin D

“…This paper describes the single event performance of a dual-complementary D-type Flip-Flop (DC-DFF) implemented similarly to Dual Interlocked Cell (DICE-DFFs),…”
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The Effects of Gamma Ray Integrated Dose on a Commercial 65nm SRAM Device by Stirk, Wesley, Black, Dolores A., Black, Jeffrey D., Breeding, Matthew, Cuoco, Roy P., Wirthlin, Mike, Goeders, Jeffrey

“…This work shows that the SRAM error rate for a commercial 65nm device in a dose rate environment can be highly dependent upon the integrated dose (dose rate ×…”
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Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing by Quinn, H. M., Black, D. A., Robinson, W. H., Buchner, S. P.

“…As of 2013, the gold standard for assessing radiation-hardness assurance (RHA) for a system, subsystem, or a component is accelerated radiation testing and/or…”
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Measuring and Modeling Single Event Transients in 12-nm Inverters by Agarwal, Sapan, Clark, Lawrence T., Youngsciortino, Clifford, Ng, Garrick, Black, Dolores, Cannon, Matthew, Black, Jeffrey, Quinn, Heather, Brunhaver, John, Barnaby, Hugh, Manuel, Jack, Blansett, Ethan, Marinella, Matthew J.

“…In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology. A test structure is presented…”
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Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors by Cannon, Matthew, Rodrigues, Arun, Black, Dolores, Black, Jeff, Bustamante, Luis, Breeding, Matthew, Feinberg, Ben, Skoufis, Micahel, Quinn, Heather, Clark, Lawrence T., Brunhaver, John, Barnaby, Hugh, McLain, Michael, Agarwal, Sapan, Marinella, Matthew J.

“…Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an…”
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DFF Layout Variations in CMOS SOI ? Analysis of Hardening by Design Options by Black, Jeffrey, Black, Dolores Archuleta, Domme, Nicholas Andrew, Dodd, Paul E., Griffin, Patrick J., Nowlin, Robert Nathaniel, Trippe, James, Salas, Joseph Gregory, Reed, Robert, Weller, Robert, Tonigan, Drew, Schrimpf, Ronald

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Using MRED to Screen Multiple Node Charge Collection Mitigated SOI Layouts by Black, Jeffrey, Dame, Jeff A., Black, Dolores Archuleta, Dodd, Paul E., Shaneyfelt, Marty R., Teifel, John, Salas, Joseph Gregory, Steinbach, Robert, Davis, Matthew, Reed, Robert A., Weller, Robert A., Trippe, James, Warren, Kevin M., Tonigan, Andrew M., Schrimpf, Ronald D., Marquez, Richard S.

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Direct ionization-induced transient fault analysis for combinational logic and sequential capture in digital integrated circuits for lightly-ionizing environments by Black, Dolores A

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Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process by Amusan, O.A., Massengill, L.W., Baze, M.P., Bhuva, B.L., Witulski, A.F., Black, J.D., Balasubramanian, A., Casey, M.C., Black, D.A., Ahlbin, J.R., Reed, R.A., McCurdy, M.W.

“…In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are…”
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