Search Results - "Bietti, I"

A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner by Valla, M., Montagna, G., Castello, R., Tonietto, R., Bietti, I.

“…A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has…”
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A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization by Rezzi, F., Bietti, I., Cazzaniga, M., Castello, R.

“…A seventh-order phase equiripple continuous time filter implementing pulse shaping and noise filtering for partial response maximum likelihood (PRML) read…”
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Experimental study and modeling of the white noise sources in submicron Pand N-MOSFETs by Re, V., Bietti, I., Castello, R., Manghisoni, M., Speziali, V., Svelto, F.

“…This paper presents the results of the experimental characterization of the channel thermal noise in MOSFETs belonging to a submicron gate process, with…”
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A 700-kHz bandwidth /Sigma//Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications by Temporiti, E, Albasini, G, Bietti, I, Castello, R, Colombo, M

“…A /Sigma//Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization…”
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A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo by Alini, R., Betti, G., Bietti, I., Bollati, G., Brianti, F., Dati, A., Demicheli, M., Gadducci, P., Marchese, S., Marconetti, E., Pisati, V., Zuffada, M., Castello, R., Heydari, F., Gillen, P., Maguire, G., Marrow, M., McDonagh, S., O'Brien, F., O'Brien, J., O'hEarcain, N., Reddy, D., Fredrickson, L., Stone, D., Volz, L.

“…A fully integrated partial response maximum likelihood (PRML) read/write IC with analog adaptive equalization operates up to 200 MSample/s. The chip implements…”
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A 2.7-V CMOS single-chip baseband processor for CT2/CT2+ cordless telephones by Crippa, C., Nicollini, G., Mecchia, A., Rizzo, P., Confalonieri, P., Pernici, S., Nagari, A., Viani, E., Bietti, I., Adduci, F., Mariani, S., Calloni, A., Moioli, M., Mandelli, S., Dallavalle, C.

“…A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec,…”
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A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter by Tonietto, R., Zuffetti, E., Castello, R., Bietti, I.

“…A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low…”
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A 700-kHz bandwidth /spl Sigma//spl Delta/ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications by Temporiti, E., Albasini, G., Bietti, I., Castello, R., Colombo, M.

“…A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization…”
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A 700-kHz bandwidth [Sigma][Delta] fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications by Temporiti, E, Albasini, G, Bietti, I, Castello, R, Colombo, M

“…With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 μs. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1…”
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A 700-kHz bandwidth capital sigma Delta fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications by Temporiti, E, Albasini, G, Bietti, I, Castello, R, Colombo, M

“…A capital sigma Delta fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization…”
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Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End by Liscidini, A., Ghezzi, C., Depaoli, E., Albasini, G., Bietti, I., Castello, R.

“…A new topology of transformer based low noise amplifier is presented. The structure realizes a low noise input match and a current gain greater than one by a…”
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A 35-mW 3.6-mm2 fully integrated 0.18-[micro]m CMOS GPS radio by Montagna, G, Gramegna, G, Bietti, I, Franciotta, M, Baschirotto, A, De Vita, P, Pelleriti, R, Paparo, M, Castello, R

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A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio by Montagna, G., Gramegna, G., Bietti, I., Franciotta, M., Baschirotto, A., De Vita, P., Pelleriti, R., Paparo, M., Castello, R.

“…A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network…”
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A 35-mW 3.6-mm/spl 2/ fully integrated 0.18-μm CMOS GPS radio by Montagna, G., Gramegna, G., Bietti, I., Franciotta, M., Baschirotto, A., De Vita, P., Pelleriti, R., Paparo, M., Castello, R.

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A 35-mW 3.6-mm(2) fully integrated 0.18-mum CMOS GPS radio by Montagna, G, Gramegna, G, Bietti, I, Franciotta, M, Baschirotto, A, De Vita, P, Pelleriti, R, Paparo, M, Castello, R

“…A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network…”
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A 35-mW 3.6-mm super(2) fully integrated 0.18- mu m CMOS GPS radio by Montagna, G, Gramegna, G, Bietti, I, Franciotta, M, Baschirotto, A, De Vita, P, Pelleriti, R, Paparo, M, Castello, R

“…A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network…”
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A multi-standard WLAN RF front-end transmitter with single-spiral dual-resonant tank loads by Albasini, G., Mori, L., Bietti, I., Castello, R.

“…This paper describes a radio frequency (RF) front end transmitter for wireless LAN (WLAN), designed for the most common standards, integrated in digital CMOS…”
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A 5mA CMOS FM Front-End with 39 dB IRR and 52 dB Channel Selectivity by Bianchi, S., Signini, M., Baschirotto, A., Bietti, I., Bona, C., Canobbio, A., Introini, M., Sacchi, E., Castello, R.

“…A complete analog front-end, with the exclusion of the frequency synthesizer, for FM broadcasting occupies 2.8 mm 2 active area in a standard 0.35 mum CMOS…”
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70 mW 7 super(th)-order filter with 7 to 50 MHz cutoff frequency, programmable boost, and group-delay equalization by Rezzi, F, Cazzaniga, M, Bietti, I, Castello, R

“…A continuous time filter has been developed for the read channel of a disk drive that uses the partial response maximum likelihood magnetic storage detection…”
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Wireless multi-standard terminals: system analysis and design of a reconfigurable RF front-end by Agnelli, F., Albasini, G., Bietti, I., Gnudi, A., Lacaita, A., Manstretta, D., Rovatti, R., Sacchi, E., Savazzi, P., Svelto, F., Temporiti, E., Vitali, S., Castello, R.

“…The availability of multi-standard terminals will be key to provide location independent connections able to take advantage of any possible infrastructure…”
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