Search Results - "Biery, G."

Competitive and cost effective copper/low-k interconnect (BEOL) for 28 nm CMOS technologies by AUGUR, R, CHILD, C, QUON, R, KIM, B, SHENG, H, HIROOKA, S, GUPTA, R, THOMAS, A, SINGH, S. M, FANG, Q, SCHIWON, R, HAMIEH, B, AHN, J. H, WORNYO, E, ALLEN, S, KALTALIOGLU, E, RIBES, G, ZHANG, G, FRYXELL, T, OGINO, A, SHIMADA, E, AIZAWA, H, MINDA, H, TANG, T. J, KIM, S. O, OKI, T, FUJII, K, PALLACHALIL, M, TAKEWAKI, T, HU, C. K, SUNDLOF, B, PERMANA, D, BOLOM, T, ENGEL, B, CLEVENGER, L, LABELLE, C, SAPP, B, NOGAMI, T, SIMON, A, SHOBHA, H, GATES, S, RYAN, E. T, BONILLA, G, DAUBENSPECK, T, SHAW, T, KIOUSSIS, D, OSBORNE, G, GRILL, A, EDELSTEIN, D, RESTAINO, D, MOLIS, S, SPOONER, T, FERREIRA, P, BIERY, G, SAMPSON, R, MASUDA, H, SRIVASTAVA, R, ODA, Y, OGUMA, H

“…A cost effective 28 nm CMOS Interconnect technology is presented for 28 nm node high performance and low power applications. Full entitlement of ultra low-k…”
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Paradoxical predictions and a minimum failure time in electromigration by Filippi, R. G., Biery, G. A., Wachnik, R. A.

“…A paradox arises when the two-parameter log-normal distribution is used to predict early electromigration lifetimes of a two-level structure with Ti–AlCu–Ti…”
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1/ f noise and electromigration in aluminum films: The role of film microstructure and texture by Smith, R. G., Biery, G. A., Rodbell, K. P.

“…The role of crystallographic texture on excess noise and the ability of excess noise to predict the electromigration behavior of pure aluminum films is…”
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Thermal cycle reliability of stacked via structures with copper metallization and an organic low-k dielectric by Filippi, R.G., McGrath, J.F., Shaw, T.M., Murray, C.E., Rathore, H.S., McLaughlin, P.S., McGahay, V., Nicholson, L., Wang, P.-C., Lloyd, J.R., Lane, M., Rosenberg, R., Liu, X., Wang, Y.-Y., Landers, W., Spooner, T., Demarest, J.J., Engel, B.H., Gill, J., Goth, G., Barth, E., Biery, G., Davis, C.R., Wachnik, R.A., Goldblatt, R., Ivers, T., Swinton, A., Barile, C., Aitken, J.

“…The reliability of a stacked via chain stressed under various thermal cycle conditions is described. The chain consists of Cu Dual Damascene metallization with…”
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Competitive and cost effective copper/low-k interconnect (BEOL) for 28nm CMOS technologies by Augur, R., Child, C., Ahn, J.H., Tang, T.J., Clevenger, L., Kioussis, D., Masuda, H., Srivastava, R., Oda, Y., Oguma, H., Quon, R., Kim, B., Sheng, H., Hirooka, S., Gupta, R., Thomas, A., Singh, S.M., Fang, Q., Schiwon, R., Hamieh, B., Wornyo, E., Allen, S., Kaltalioglu, E., Ribes, G., Zhang, G., Fryxell, T., Ogino, A., Shimada, E., Aizawa, H., Minda, H., Kim, S.O., Oki, T., Fujii, K., Pallachalil, M., Takewaki, T., Hu, C.K., Sundlof, B., Permana, D., Bolom, T., Engel, B., Labelle, C., Sapp, B., Nogami, T., Simon, A., Shobha, H., Gates, S., Ryan, E.T., Bonilla, G., Daubenspeck, T., Shaw, T., Osborne, G., Grill, A., Edelstein, D., Restaino, D., Molis, S., Spooner, T., Ferreira, P., Biery, G., Sampson, R.

“…A cost effective 28nm CMOS Interconnect technology is presented for 28nm node high performance and low power applications. Full entitlement of ultra low-k…”
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A 7nm CMOS technology platform for mobile and high performance compute application by Zhao, K., Morganfeld, B., Dechene, J., Radens, C., Tessier, A., Hassan, A., Narisetty, H., Ahsan, I., Aquilino, M., Augur, R., Baliga, N., Blauberg, A., Borjemscaia, N., Bryant, A., Chauhan, V., Chen, M., Choo, J., Chu, T., Coleman, R., Conklin, D., Dechene, D., Derderian, G., Deshpande, S., Dilliway, G., Donegan, K., Eller, M., Fan, Y., Gassaria, A., Gauthier, R., Ghosh, S., Gifford, G., Gribelyuk, M., Han, G., Han, J. H., Hasan, M., Hu, L., Hung, T., Jin, Y., Johnson, J., Johnson, S., Joshi, M., Kalaga, S., Kim, T., Kim, W., Krishnan, R., Anil, K., Lee, J., Lee, R., Lemon, J., Liew, S. L., Lindo, P., Lingalugari, M., Liu, P., Liu, J., Lucarini, S., Ma, W., Maciejewski, E., Madisetti, S., Malinowski, A., Mehta, J., Meng, C., Mitra, S., Nayfeh, H., Nigam, T., Northrop, G., Ordonio, C., Ozbek, M., Pal, R., Parihar, S., Patterson, O., Ramanathan, E., Ramirez, I., Sarad, J., Saudari, S., Serrau, C., Shen, T., Sheng, H., Shepard, J., Shi, Y., Silvestre, M. C., Singh, D., Song, Z., Sporre, J., Srinivasan, P., Sun, Z., Sutton, A., Sweeney, R., Tan, M., Xu, D., Xuan, T., Yu, M., Zainuddin, A., Zhang, K., Zhao, M., Lin, C.-H, Grunow, S., Fox, R., Kaste, E., Gomba, G., Sohn, D. K.

“…We present a fully integrated 7nm CMOS platform featuring a 3 rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This…”
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Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections by Deutsch, A., Harrer, H., Surovic, C.W., Hellner, G., Edelstein, D.C., Goldblatt, R.D., Biery, G.A., Greco, N.A., Foster, D.M., Crabbe, E., Su, L.T., Coteus, P.W.

“…Experimental high-speed characterization and electrical modeling and simulation are presented for a six-layer Cu/SiO/sub 2/ on-chip wiring structure with…”
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The importance of educating kidney transplant patients and their families about the surgery, before the operation by Biery-Hamilton, G M

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Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics : Enhanced performance at reduced gate leakage by GUSEV, E. P, CABRAL, C. JR, CALLEGARI, A, CARRUTHERS, R, COHEN, S. A, COPEL, M, FANG, S, FRANK, M, GUHA, S, GRIBELYUK, M, JAMISON, P, JAMMY, R, LINDER, B. P, IEONG, M, KEDZIERSKI, J, KOZLOWSKI, P, KU, V, LACEY, D, LATULIPE, D, NARAYANAN, V, NG, H, NGUYEN, P, NEWBURY, J, KIM, Y. H, PARUCHURI, V, RENGARAJAN, R, SHAHIDI, G, STEEGEN, A, STEEN, M, ZAFAR, S, ZHANG, Y, MAITRA, K, CARTIER, E, NAYFEH, H, AMOS, R, BIERY, G, BOJARCZUK, N

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A 45 nm CMOS node Cu/Low-k/ Ultra Low-k PECVD SiCOH (k=2.4) BEOL Technology by Sankaran, S., Arai, S., Augur, R., Beck, M., Biery, G., Bolom, T., Bonilla, G., Bravo, O., Chanda, K., Chae, M., Chen, F., Clevenger, L., Cohen, S., Cowley, A., Davis, P., Demarest, J., Doyle, J., Dimitrakopoulos, C., Economikos, L., Edelstein, D., Farooq, M., Filippi, R., Fitzsimmons, J., Fuller, N., Gates, S.M., Greco, S.E., Grill, A., Grunow, S., Hannon, R., Ida, K., Jung, D., Kaltalioglu, E., Kelling, M., Ko, T., Kumar, K., Labelle, C., Landis, H., Lane, M.W., Landers, W., Lee, M., Li, W., Liniger, E., Liu, X., Lloyd, J.R., Liu, W., Lustig, N., Malone, K., Marokkey, S., Matusiewicz, G., McLaughlin, P.S., McLaughlin, P.V., Mehta, S., Melville, I., Miyata, K., Moon, B., Nitta, S., Nguyen, D., Nicholson, L., Nielsen, D., Ong, P., Patel, K., Patel, V., Park, W., Pellerin, J., Ponoth, S., Petrarca, K., Rath, D., Restaino, D., Rhee, S., Ryan, E.T., Shoba, H., Simon, A., Simonyi, E., Shaw, T.M., Spooner, T., Standaert, T., Sucharitaves, J., Tian, C., Wendt, H., Werking, J., Widodo, J., Wiggins, L., Wisnieff, R., Ivers, T.

“…A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in…”
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Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage by Gusev, E.P., Cabral, C., Under, B.P., Kim, Y.H., Maitra, K., Carrier, E., Nayfeh, H., Amos, R., Biery, G., Bojarczuk, N., Callegari, A., Carruthers, R., Cohen, S.A., Copel, M., Fang, S., Frank, M., Guha, S., Gribelyuk, M., Jamison, P., Jammy, R., Ieong, M., Kedzierski, J., Kozlowski, P., Ku, K., Lacey, D., LaTulipe, D., Narayanan, V., Ng, H., Nguyen, P., Newbury, J., Paruchuri, V., Rengarajan, R., Shahidi, G., Steegen, A., Steen, M., Zafar, S., Zhang, Y.

“…The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive…”
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High performance 0.18 /spl mu/m SOI CMOS technology by Leobandung, E., Barth, E., Sherony, M., Lo, S.-H., Schulz, R., Chu, W., Khare, M., Sadana, D., Schepis, D., Boiam, R., Sleight, I., White, F., Assaderaghi, F., Moy, D., Biery, G., Goldblan, R., Chen, T.-C., Davari, B., Shahidi, G.

“…A 0.18 /spl mu/m SOI CMOS technology is presented. Key features in this technology are: more aggressive gate lithography (equivalent to 0.15 /spl mu/m half…”
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A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL by Sleight, J.W., Varekamp, P.R., Lustig, N., Adkisson, J., Allen, A., Bula, O., Chen, X., Chou, T., Chu, W., Fitzsimmons, J., Gabor, A., Gates, S., Jamison, P., Khare, M., Lai, L., Lee, J., Narasimha, S., Ellis-Monaghan, J., Peterson, K., Rauch, S., Shukla, S., Smeys, P., Su, T.-C., Quinlan, J., Vayshenker, A., Ward, B., Womack, S., Barth, E., Biery, G., Davis, C., Ferguson, R., Goldblatt, R., Leobandung, E., Weiser, J., Yang, I., Agnello, P.

“…This paper describes a second generation 1.2 V high performance 0.13 /spl mu/m SOI technology. Aggressive ground rules and a tungsten damascene local…”
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A 0.18 /spl mu/m high-performance logic technology by Crowder, S., Greco, S., Ng, H., Barth, E., Beyer, K., Biery, G., Connolly, J., DeWan, C., Ferguson, R., Chen, X., Hargrove, M., Nowak, E., McLaughlin, P., Purtell, R., Logan, R., Oberschmidt, J., Ray, A., Ryan, D., Tallman, K., Wagner, T., McGahay, V., Crabbe, E., Agnello, P., Goldblatt, R., Su, L., Davari, B.

“…In this paper, we describe a high-performance 0.18 /spl mu/m logic technology with dual damascene copper metallization and dense SRAM memory. Local…”
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A high-performance sub-0.25 /spl mu/m CMOS technology with multiple thresholds and copper interconnects by Su, L., Schulz, R., Adkisson, J., Beyer, K., Biery, G., Cote, W., Crabbe, E., Edelstein, D., Ellis-Monaghan, J., Eld, E., Foster, D., Gehres, R., Goldblatt, R., Greco, N., Guenther, C., Heidenreich, J., Herman, J., Kiesling, D., Lin, L., Lo, S.-H., McKenna, J., Megivern, C., Ng, H., Oberschmidt, J., Ray, A., Rohrer, N., Tallman, K., Wagner, T., Davari, B.

“…A sub-0.25 /spl mu/m technology in manufacturing that is targeted for high-performance CMOS applications is discussed. Aggressive groundrule scaling including…”
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