Search Results - "Bhoraskar, Paritosh"

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Bardsley, Scott, Dillon, Chris, McShea, Matthew, Periathambi, Joel Prabhakar, Puckett, Scott

“…We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold…”
Get full text

A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Dillon, Chris, Puckett, Scott, Gray, Bryce, Speir, Carroll, Lanford, Jonathan, Brunsilius, Janet, Derounian, Peter R., Jeffries, Brad, Mehta, Ushma, McShea, Matthew, Stop, Russell

“…We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and…”
Get full text

16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Bardsley, Scott, Dillon, Chris, Kumar, Mohit, McShea, Matthew, Bunch, Ryan, Prabhakar, Joel, Puckett, Scott

“…High sample rate ADCs with high input bandwidth and low power consumption enable direct RF sampling, more integration, flexibility and lower cost for…”
Get full text

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration by Ali, A M A, Morgan, A, Dillon, C, Patterson, G, Puckett, S, Bhoraskar, P, Dinc, H, Hensley, M, Stop, R, Bardsley, S, Lattimore, D, Bray, J, Speir, C, Sneed, R

“…This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that…”
Get full text

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration by Ali, A.M.A., Morgan, A., Dillon, C., Patterson, G., Puckett, S., Hensley, M., Stop, R., Bhoraskar, P., Bardsley, S., Lattimore, D., Bray, J., Speir, C., Sneed, R.

“…We present a 16b 250MS/S ADC that employs background calibration of the residue amplifier gain errors. It has an integrated input buffer and is fabricated on a…”
Get full text

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Dillon, Chris, Puckett, Scott, Gray, Bryce, Speir, Carroll, Lanford, Jonathan, Jarman, David, Brunsilius, Janet, Derounian, Peter, Jeffries, Brad, Mehta, Ushma, McShea, Matt, Ho-Young Lee

“…We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory…”
Get full text

A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Puckett, Scott, Morgan, Andy, Ning Zhu, Yu Qicheng, Dillon, Chris, Gray, Bryce, Lanford, Jon, McShea, Matt, Mehta, Ushma, Bardsley, Scott, Derounian, Peter, Bunch, Ryan, Moore, Ralph, Taylor, Gerry

“…We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling…”
Get full text

A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector by Bhoraskar, P., Yun Chiu

“…A 0.13-mum CMOS dual-loop digital DLL for multiphase clock generation and synchronization is presented. Ten clock phases are produced and locked to a first…”
Get full text