Search Results - "Bhoraskar, P"

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration by Ali, A M A, Morgan, A, Dillon, C, Patterson, G, Puckett, S, Bhoraskar, P, Dinc, H, Hensley, M, Stop, R, Bardsley, S, Lattimore, D, Bray, J, Speir, C, Sneed, R

“…This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that…”
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A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration by Ali, A.M.A., Morgan, A., Dillon, C., Patterson, G., Puckett, S., Hensley, M., Stop, R., Bhoraskar, P., Bardsley, S., Lattimore, D., Bray, J., Speir, C., Sneed, R.

“…We present a 16b 250MS/S ADC that employs background calibration of the residue amplifier gain errors. It has an integrated input buffer and is fabricated on a…”
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A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector by Bhoraskar, P., Yun Chiu

“…A 0.13-mum CMOS dual-loop digital DLL for multiphase clock generation and synchronization is presented. Ten clock phases are produced and locked to a first…”
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