Multi-VT engineering in highly scaled CMOS bulk and FinFET devices through Ion Implantation into the metal gate stack featuring a 1.0nm EOT high-K oxide

We demonstrate multi-V T engineering on both CMOS bulk and FinFET devices through As implantation into a 1.0nm EOT TiN/high-K gate stack within a single metal single dielectric approach. We determine a As implantation process window enabling V T tuning without any device degradation. It is shown tha...

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Bibliographic Details
Published in:	Proceedings of 2010 International Symposium on VLSI Technology, System and Application pp. 112 - 113
Main Authors:	Singanamalla, R, Boccardi, G, Tseng, J, Petry, J, Vellianitis, G, van Dal, M J H, Duriez, B, Vecchio, G, Bulle-Lieuwma, C W T, Berkum, J V, Lander, R, Müller, M
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-04-2010
Subjects:	Degradation Dielectric devices Doping FinFETs Hafnium oxide High K dielectric materials High-K gate dielectrics Ion implantation MOS devices Tin
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Summary:	We demonstrate multi-V T engineering on both CMOS bulk and FinFET devices through As implantation into a 1.0nm EOT TiN/high-K gate stack within a single metal single dielectric approach. We determine a As implantation process window enabling V T tuning without any device degradation. It is shown that this approach is suitable for multi-V T engineering with aggressively scaled dielectrics and, particularly, for fully depleted 3D device architectures.
ISBN:	9781424450633 1424450632
ISSN:	1524-766X 2690-8174
DOI:	10.1109/VTSA.2010.5488925