Search Results - "Becer, M.R."
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1
Postroute gate sizing for crosstalk noise reduction
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-12-2004)“…Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs…”
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Journal Article -
2
Early probabilistic noise estimation for capacitively coupled interconnects
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-03-2003)“…One of the critical challenges in today's high-performance IC design is to take noise into account as early as possible in the design cycle. Current noise…”
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Journal Article -
3
Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002 (2002)“…Noise estimation and avoidance are becoming critical, 'must have' capabilities in today's high performance IC design. An accurate yet efficient crosstalk noise…”
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Conference Proceeding
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4
Post-route gate sizing for crosstalk noise reduction
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003 (02-06-2003)“…Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The…”
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Conference Proceeding -
5
Delay noise pessimism reduction by logic correlations
Published in IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 (07-11-2004)“…High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static…”
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Conference Proceeding -
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Pre-route noise estimation in deep submicron integrated circuits
Published in Proceedings International Symposium on Quality Electronic Design (2002)“…One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise…”
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Conference Proceeding -
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Post-route gate sizing for crosstalk noise reduction
Published in Fourth International Symposium on Quality Electronic Design, 2003. Proceedings (2003)“…Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs…”
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Conference Proceeding -
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A global driver sizing tool for functional crosstalk noise avoidance
Published in Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design (2001)“…As coupling noise analysis and estimation is reaching a relative maturity with recent efforts, more effort is needed in correcting and/or avoiding failures…”
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Conference Proceeding