Search Results - "Becer, M."

Crosstalk noise control in an SoC physical design flow by Becer, M., Vaidyanathan, R., Oh, C., Panda, R.

“…Signal integrity closure is one of the key challenges in deep submicron physical design. In this paper, we propose a physical design methodology which includes…”
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Cutis Laxa with Growth and Developmental Delay by Karakurt, C., Sipahi, T, Ceylaner, S., Senocak, F, Karademir, S., Becer, M.

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Postroute gate sizing for crosstalk noise reduction by Becer, M.R., Blaauw, D., Algor, I., Panda, R., Oh, C., Zolotov, V., Hajj, I.N.

“…Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs…”
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Early probabilistic noise estimation for capacitively coupled interconnects by Becer, M.R., Blaauw, D., Panda, R., Hajj, I.N.

“…One of the critical challenges in today's high-performance IC design is to take noise into account as early as possible in the design cycle. Current noise…”
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False-noise analysis for domino circuits by Glebov, A., Gavrilov, S., Zolotov, V., Chanhee Oh, Panda, R., Becer, M.

“…High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use…”
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Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model by Becer, M.R., Blaauw, D., Zolotov, V., Panda, R., Hajj, I.N.

“…Noise estimation and avoidance are becoming critical, 'must have' capabilities in today's high performance IC design. An accurate yet efficient crosstalk noise…”
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Gastric leiomyoblastoma: report of three cases by Atalay, C, Becer, M, Ozaslan, C, Pak, I, Altinok, M

“…Leiomyoblastoma is a rare smooth muscle tumor characterized by epithelioid cells with clear cytoplasms and an unknown biological behaviour. Since pre-operative…”
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Delay noise pessimism reduction by logic correlations by Glebov, A., Gavrilov, S., Soloviev, R., Zolotov, V., Becer, M. R., Oh, C., Panda, R.

“…High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static…”
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Pessimism reduction in crosstalk noise aware STA by Becer, M., Zolotov, V., Panda, R., Grinshpon, A., Algol, I., Levy, R., Oh, C.

“…High performance circuits are facing increasingly severe signal integrity problems due to crosstalk noise and crosstalk noise awareness has become an integral…”
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Noise propagation and failure criteria for VLSI designs by Zolotov, V., Blaauw, D., Sirichotiyakul, S., Becer, M., Oh, C., Panda, R., Grinshpon, A., Levy, R.

“…Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated…”
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Transistor level gate modeling for accurate and fast timing, noise, and power analysis by Raja, S., Varadi, F., Becer, M., Geada, J.

“…Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly…”
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An analytical model for delay and crosstalk estimation in interconnects under general switching conditions by Becer, M., Hajj, I.N.

“…The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In timing analysis, the…”
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Pessimism reduction in crosstalk noise aware STA by Becer, M., Zolotov, V., Panda, R., Grinshpon, A., Algol, I., Levy, R., Oh, C.

“…High performance circuits are facing increasingly severe signal integrity problems due to crosstalk noise and crosstalk noise awareness has become an integral…”
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SOI Transistor Model for Fast Transient Simulation by Nadezhin, D., Gavrilov, S., Glebov, A., Egorov, Y., Zolotov, V., Blaauw, D., Panda, R., Becer, M., Ardelea, A., Patel, A.

“…Progress in semiconductor process technology has made SOItransistors one of the most promising candidates for high performanceand low power designs. With…”
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Static electromigration analysis for signal interconnects by Chanhee Oh, Blaauw, D., Becer, M., Zolotov, V., Panda, R., Dasgupta, A.

“…With the increase in current densities, electromigration has become a critical concern in high-performance designs. Typically, electromigration has involved…”
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Pre-route noise estimation in deep submicron integrated circuits by Becer, M.R., Blaauw, D., Panda, R., Hajj, I.N.

“…One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise…”
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Top-k aggressors sets in delay noise analysis by Gandikota, Ravikishore, Chopra, Kaviraj, Blaauw, David, Sylvester, Dennis, Becer, Murat

“…We present, in this paper, novel algorithms to compute the set of "top-k" aggressors in a design. We show that the computation of the set of top-k aggressors…”
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Cerebro-oculo-facio-skeletal syndrome: report of two cases from Turkey with postmortem findings by Semerci, C Nur, Onat, Neşe, Günçe, Sevil, Demirel, Nihal, Yilmazer, Murat Becer Yanki, Oznur, Izlem, Türkyilmaz, Canan, Balci, Sevim

“…We describe two cases of COFS (cerebro-oculo-facio-skeletal) syndrome in two newborn females of consanguineous parents. The clinical, radiological and…”
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Victim alignment in crosstalk aware timing analysis by Gandikota, R., Chopra, K., Blaauw, D., Sylvester, D., Becer, M., Joao Geada

“…Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the "victim-aggressor alignment" problem. As…”
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An analytical model for delay and crosstalk estimation with application to decoupling by Becer, M., Hajj, I.N.

“…The impact of interconnect coupling, in the form of delay and crosstalk, in deep submicron integrated circuit design is increasing. In many cases, especially…”
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