Search Results - "Beattie, M.W."
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Parasitics extraction with multipole refinement
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-02-2004)“…Modern chip design pushes the performance of a given technology to its limits, therefore, it is necessary to find increasingly more accurate models for…”
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Journal Article -
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On-chip induction modeling: basics and advanced methods
Published in IEEE transactions on very large scale integration (VLSI) systems (01-12-2002)“…Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for integrated circuit design in recent years. This paper…”
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Journal Article -
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Inductance 101: modeling and extraction
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 38th conference on Design automation (01-01-2001)“…Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for inte-grated circuit design in recent years. This tutorial…”
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Conference Proceeding
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Modeling magnetic coupling for on-chip interconnect
Published in Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) (01-01-2001)“…As advances in IC technologies and operat-ing frequencies make the modeling of on-chip magnetic interactions a necessity, it is apparent that extension of…”
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Conference Proceeding -
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Bounds For BEM Capacitance Extraction
Published in Proceedings of the 34th Design Automation Conference (1997)Get full text
Conference Proceeding -
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Error bounds for capacitance extraction via window techniques
Published in IEEE transactions on computer-aided design of integrated circuits and systems (01-03-1999)“…The overwhelming size of the capacitance extraction problem forces designers to localize the capacitive coupling and determine a distance (a "window") outside…”
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IC analyses including extracted inductance models
Published in Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361) (1999)“…IC inductance extraction generally produces either port inductances based on simplified current path assumptions or a complete partial inductance matrix…”
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Conference Proceeding -
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On-chip inductance models: 3D or not 3D?
Published in Design, Automation, and Test in Europe: Proceedings of the conference on Design, automation and test in Europe; 04-08 Mar. 2002 (2002)“…Full 3D lumped partial inductance models usually contain a tremendous amount of forward coupling terms. To reduce the complexity of simulation and analysis, a…”
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Conference Proceeding -
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Electromagnetic parasitic extraction via a multipole method with hierarchical refinement
Published in 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051) (1999)“…The increasing interconnect density and operating frequencies of system-on-a-chip (SOC) designs necessitates extraction of parasitic electromagnetic couplings…”
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Conference Proceeding Journal Article