Search Results - "Baylac, E."

Ultrathin (5nm) SiGe-On-Insulator with high compressive strain (−2GPa): From fabrication (Ge enrichment process) to in-depth characterizations by Glowacki, F., Le Royer, C., Morand, Y., Pédini, J.-M., Denneulin, T., Cooper, D., Barnes, J.-P., Nguyen, P., Rouchon, D., Hartmann, J.-M., Gourhant, O., Baylac, E., Campidelli, Y., Barge, D., Bonnin, O., Schwarzenbach, W.

“…300mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5nm thick SiGe-On-Insulator…”
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14nm FDSOI technology for high speed and energy efficient applications by Weber, O., Josse, E., Andrieu, F., Cros, A., Richard, E., Perreau, P., Baylac, E., Degors, N., Gallon, C., Perrin, E., Chhun, S., Petitprez, E., Delmedico, S., Simon, J., Druais, G., Lasserre, S., Mazurier, J., Guillot, N., Bernard, E., Bianchini, R., Parmigiani, L., Gerard, X., Pribat, C., Gourhant, O., Abbate, F., Gaumer, C., Beugin, V., Gouraud, P., Maury, P., Lagrasta, S., Barge, D., Loubet, N., Beneyton, R., Benoit, D., Zoll, S., Chapon, J.-D., Babaud, L., Bidaud, M., Gregoire, M., Monget, C., Le-Gratiet, B., Brun, P., Mellier, M., Pofelski, A., Clement, L.R., Bingert, R., Puget, S., Kruck, J.-F., Hoguet, D., Scheer, P., Poiroux, T., Manceau, J.-P., Rafik, M., Rideau, D., Jaud, M.-A., Lacord, J., Monsieur, F., Grenouillet, L., Vinet, M., Liu, Q., Doris, B., Celik, M., Fetterolf, S.P., Faynot, O., Haond, M.

“…This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm…”
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Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET by Berthelon, R., Andrieu, F., Ortolland, S., Nicolas, R., Poiroux, T., Baylac, E., Dutartre, D., Josse, E., Claverie, A., Haond, M.

“…The introduction of SiGe channel for pMOSFETs in FDSOI technology enables to achieve high performance. However, it has been demonstrated that such a global…”
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Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14nm UTBB FDSOI technology by Berthelon, R., Andrieu, F., Ortolland, S., Nicolas, R., Poiroux, T., Baylac, E., Dutartre, D., Josse, E., Claverie, A., Haond, M.

“…The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB…”
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Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration by Berthelon, R., Andrieu, F., Perreau, P., Baylac, E., Pofelski, A., Josse, E., Dutartre, D., Claverie, A., Haond, M.

“…We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first…”
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Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs by Berthelon, R., Andrieu, F., Josse, E., Bingert, R., Weber, O., Serret, E., Aurand, A., Delmedico, S., Farys, V., Bernicot, C., Bechet, E., Bernard, E., Poiroux, T., Rideau, D., Scheer, P., Baylac, E., Perreau, P., Jaud, M. A., Lacord, J., Petitprez, E., Pofelski, A., Ortolland, S., Sardin, P., Dutartre, D., Claverie, A., Vinet, M., Marin, J. C., Haond, M.

“…We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This…”
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Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs by Andrieu, F., Casse, M., Baylac, E., Perreau, P., Nier, O., Rideau, D., Berthelon, R., Pourchon, F., Pofelski, A., De Salvo, B., Gallon, C., Mazzocchi, V., Barge, D., Gaumer, C., Gourhant, O., Cros, A., Barral, V., Ranica, R., Planes, N., Schwarzenbach, W., Richard, E., Josse, E., Weber, O., Arnaud, F., Vinet, M., Faynot, O., Haond, M.

“…We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (I ON ) and +18%…”
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A novel dual isolation scheme for stress and back-bias maximum efficiency in FDSOI Technology by Berthelon, R., Andrieu, F., Perreau, P., Cooper, D., Roze, F., Gourhant, O., Rivallin, P., Bernier, N., Cros, A., Ndiaye, C., Baylac, E., Souchier, E., Dutartre, D., Claverie, A., Weber, O., Josse, E., Vinet, M., Haond, M.

“…A novel dual isolation scheme with both Shallow Trench Isolation (STI) and local oxidation, so called Dual Isolation by Trenches and Oxidation (DITO), is…”
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A Cost-Effective Low Power Platform for the 45-nm Technology Node by Josse, E., Parihar, S., Callen, O., Ferreira, P., Monget, C., Farcy, A., Zaleski, M., Villanueva, D., Ranica, R., Bidaud, M., Barge, D., Laviron, C., Auriac, N., Le Cam, C., Harrison, S., Warrick, S., Leverd, F., Gouraud, P., Zoll, S., Guyader, F., Perrin, E., Baylac, E., Belledent, J., Icard, B., Minghetti, B., Manakli, S., Pain, L., Huard, V., Ribes, G., Rochereau, K., Bordez, S., Blanc, C., Margain, A., Delille, D., Pantel, R., Barla, K., Cave, N., Haond, M.

“…This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This…”
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