Search Results - "Baureis, P."

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  1. 1

    Compact modeling of electrical, thermal and optical LED behavior by Baureis, P.

    “…A new nonlinear compact LED model for circuit simulators like SPICE or ADS is presented. The model is useful to predict the LED's voltage-current…”
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    Conference Proceeding
  2. 2

    Correcting the Output Conductance for Self-Heating in InAlAs/InGaAs HBTs by Weib, O., Baureis, P., Kellmann, N., Weber, N., Weigel, R.

    Published in IEEE transactions on electron devices (01-09-2006)
    “…Two methods to correct the output characteristics of a heterojunction bipolar transistor (HBT) for self-heating, which especially suit material systems with…”
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    Journal Article
  3. 3

    A simple method for the thermal resistance measurement of AlGaAs/GaAs heterojunction bipolar transistors by Bovolon, N., Baureis, P., Muller, J.-E., Zwicknagl, P., Schultheis, R., Zanoni, E.

    Published in IEEE transactions on electron devices (01-08-1998)
    “…A novel electrical method to accurately measure the thermal resistance of heterojunction bipolar transistors (HBT's) is presented. The key advantage of the…”
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    Journal Article
  4. 4

    A new compact model for the avalanche effect in InAlAs/InGaAs HBTs by Weiss, O., Baureis, P., Kellmann, N., Weber, N., Weigel, R.

    Published in IEEE electron device letters (01-06-2006)
    “…This letter presents a new compact model for the avalanche effect in InAlAs/InGaAs heterojunction bipolar transistors. Unlike previous models, it is based on…”
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    Journal Article
  5. 5

    Obtaining isothermal data for HBT by Fregonese, S., Zimmer, T., Mnif, H., Baureis, P., Maneux, C.

    Published in IEEE transactions on electron devices (01-07-2004)
    “…A new measurement method to obtain isothermal electrical characteristics is presented. Heterojunction bipolar transistor (HBT) dc and S-parameter measurements…”
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    Journal Article
  6. 6

    New transmission line structure with suppressed eddy current effects by Peter, M., Hein, H., Oehler, F., Baureis, P.

    “…A new transmission line structure is presented which features suppression of eddy currents and skin-effect. This results in lower loss and lower frequency…”
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    Conference Proceeding Journal Article
  7. 7

    A small chip size 2 W, 62% efficient HBT MMIC for 3 V PCN applications by Muller, J.-E., Baureis, P., Berger, O., Boettner, T., Bovolon, N., Schultheis, R., Packeiser, G., Zwicknagl, P.

    Published in IEEE journal of solid-state circuits (01-09-1998)
    “…This work describes the L-band low voltage (/spl ges/1.6 V) power performance of AlGAs/GaAs heterojunction bipolar transistors (HBTs), their modeling and the…”
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    Journal Article
  8. 8

    A 2.4-GHz ISM-transmitter IC with novel quadrature clock generation technique for a localization application by Popken, G., Baureis, P., Hartmann, M., Milosiu, H., Neubauer, H., Oehler, F., Peter, M.

    “…The design of a fully integrated 2.4-GHz ISM-band transmitter for a localization application is presented. The signal path includes DAC, anti-alias filter,…”
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    Conference Proceeding
  9. 9

    Planar inductors with subdivided conductors for reducing eddy current effects by Peter, M., Hein, H., Oehler, F., Baureis, P.

    “…In this work, a method for reducing eddy current effects in planar inductors is presented. This patent pending method has already been demonstrated to be…”
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    Conference Proceeding
  10. 10

    Parameter extraction for HBT's temperature dependent large signal equivalent circuit model [MMIC oscillator] by Baureis, P., Seitzer, D.

    Published in 15th Annual GaAs IC Symposium (1993)
    “…An eleven node large signal heterojunction bipolar transistors (HBT) model in hybrid-/spl pi/ configuration is investigated which is derived from HBT topology…”
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    Conference Proceeding
  11. 11

    A 4 Gs/s comparator fabricated in an AlGaAs/GaAs heterojunction bipolar process by Cepl, F., Baureis, P., Seitzer, D., Zwicknagl, P.

    “…A comparator circuit fabricated in an AlGaAs/GaAs heterojunction bipolar process is described. Nonlinear current gain, thermal effects, and parasitic base…”
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    Conference Proceeding
  12. 12

    Electrothermal modeling of multi-emitter heterojunction-bipolar-transistors (HBTs) by Baureis, P.

    “…A large signal equivalent circuit model for multi-emitter HBTs is proposed. The model is based on the description of a single-emitter-finger HBT which includes…”
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    Conference Proceeding
  13. 13

    A small chip size 2 W, 62%25 efficient HBT MMIC for 3 V PCNapplications by Muller, J-E, Baureis, P, Berger, O, Boettner, T, Bovolon, N, Schultheis, R, Packeiser, G, Zwicknagl, P

    Published in IEEE journal of solid-state circuits (01-09-1998)
    “…This work describes the L-band low voltage ( 1.6 V) power performance of AlGAs/GaAs heterojunction bipolar transistors (HBTs), their modeling and the design of…”
    Get full text
    Journal Article
  14. 14
  15. 15

    A new large signal model for heterojunction bipolar transistors including temperature effects by Baureis, P., McKinley, W., Seitzer, D.

    “…The authors describe an eight-node heterojunction bipolar transistor model suitable for circuit simulation, for which the Gummel-Poon model was used as a…”
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    Conference Proceeding
  16. 16

    A fully integrated 0.35 /spl mu/m CMOS MMIC amplifier for short range 433 MHz ISM band transceiver applications by Baureis, P., Hein, H., Peter, M., Oehler, F.

    “…A two-stage amplifier is implemented by utilizing Austria Micro System (AMS) 0.35 /spl mu/m CMOS technology with double poly and triple metal layers. The…”
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    Conference Proceeding
  17. 17
  18. 18

    Low phase noise low power 4.3 GHz VCO in standard 0.35 /spl mu/m CMOS by Peter, M., Hein, H., Oehler, F., Baureis, P.

    “…Good phase noise performance of an integrated 4.3 GHz VCO, implemented in a standard, digital 0.35 /spl mu/m CMOS process is reported. Measured phase noise at…”
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    Conference Proceeding
  19. 19

    Fully integrated 2-stage power amplifier module for 2.4 GHz ISM-band applications realised on 1mm2digital CMOS technology by Baureis, P., Peter, M., Oehler, F., Hein, H.

    “…The design environment together with measurement and simulation results are presented for a two stage medium power amplifier (MPA) module realised in digital…”
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    Conference Proceeding
  20. 20

    Design procedure for fully integrated 900 MHz medium power amplifiers in 0.6 /spl mu/m CMOS technology on latchup resistant epi-substrate by Baureis, P., Peter, M., Hein, H., Oehler, F.

    “…A design procedure is developed for the integration of RF-circuits in a 0.6 /spl mu/m CMOS process on latchup resistant epi-substrates. The proposed method was…”
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    Conference Proceeding