Search Results - "Baumann, F.H."

An approach to quantitative high-resolution transmission electron microscopy of crystalline materials by Kisielowski, C., Schwander, P., Baumann, F.H., Seibt, M., Kim, Y., Ourmazd, A.

“…We describe how lattice images may be used to measure the variation of the projected potential in crystalline solids in any projection, with no knowledge of…”
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Impact of gate-poly grain structure on the gate-oxide reliability [CMOS] by Kamgar, A., Vaidya, H.M., Baumann, F.H., Nakahara, S.

“…Time dependent dielectric breakdown of thin oxides, 1.5 to 5.0 nm has been studied for different gate-poly grain structures. The poly grain was varied by the…”
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Real-space analysis of lattice images and its link to conventional theory by Maurice, J.-L., Schwander, P., Baumann, F.H., Ourmazd, A.

“…We show that real-space analysis of lattice images in terms of multidimensional vectors rests on a small number of physically significant dimensions, each…”
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Thickness dependence of boron penetration through O/sub 2/- and N/sub 2/O-grown gate oxides and its impact on threshold voltage variation by Krisch, K.S., Green, M.L., Baumann, F.H., Brasen, D., Feldman, L.C., Manchanda, L.

“…We report on a quantitative study of boron penetration from p/sup +/ polysilicon through 5- to 8-nm gate dielectrics prepared by rapid thermal oxidation in…”
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Depth profiling of vacancy clusters in MeV-implanted Si using Au labeling by Venezia, V. C., Eaglesham, D. J., Haynes, T. E., Agarwal, Aditya, Jacobson, D. C., Gossmann, H.-J., Baumann, F. H.

“…A technique for profiling the clustered-vacancy region produced by high-energy ion implantation into silicon is described and tested. This technique takes…”
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Low leakage, ultra-thin gate oxides for extremely high performance sub-100 nm nMOSFETs by Timp, G., Agarwal, A., Baumann, F.H., Boone, T., Buonanno, M., Cirelli, R., Donnelly, V., Foad, M., Grant, D., Green, M., Gossmann, H., Hillenius, S., Jackson, J., Jacobson, D., Kleiman, R., Komblit, A., Klemens, F., Lee, J.T.-C., Mansfield, W., Moccio, S., Murrell, A., O'Malley, M., Rosamilia, J., Sapjeta, J., Silverman, P., Sorsch, T., Tai, W.W., Tennant, D., Vuong, H., Weir, B.

“…Reports measurements of the DC characteristics of sub-100 nm nMOSFETs that employ low leakage ultra-thin gate oxides only 1-2 nm thick to achieve high current…”
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Progress toward 10 nm CMOS devices by Timp, G., Bourdelle, K.K., Bower, J.E., Baumann, F.H., Boone, T., Cirelli, R., Evans-Lutterodt, K., Garno, J., Ghetti, A., Gossmann, H., Green, M., Jacobson, D., Kim, Y., Kleiman, R., Klemens, F., Kornlit, A., Lochstampfor, C., Mansfield, W., Moccio, S., Muller, D.A., Ocola, I.E., O'Malley, M.I., Rosamilia, J., Sapjeta, J., Silverman, P., Sorsch, T., Tennant, D.M., Timp, W., Weir, B.E.

“…One of the primary means for improving performance and increasing the scale of integration on a chip is the miniaturization of the electronic devices that…”
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On the dynamic resistance and reliability of phase change memory by Rajendran, B., Lee, M.-H., Breitwisch, M., Burr, G.W., Shih, Y.-H., Cheek, R., Schrott, A., Chen, C.-F., Lamorey, M., Joseph, E., Zhu, Y., Dasaka, R., Flaitz, P.L., Baumann, F.H., Lung, H.-L., Lam, C.

“…A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this…”
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Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs by Esseni, D., Mastrapasqua, M., Celler, G.K., Baumann, F.H., Fiegna, C., Selmi, L., Sangiorgi, E.

“…Electron and hole effective mobilities of ultra-thin SOI N- and P-MOSFETs have been measured at different temperatures using a special test structure able to…”
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Effect of implant damage on the gate oxide thickness by Vuong, H.-H, Bude, J, Baumann, F.H, Evans-Lutterodt, K, Ning, J, Ma, Y, Mcmacken, J, Gossmann, H.-J, Silverman, P, Rafferty, C.S, Hillenius, S.J

“…Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance–voltage ( C– V) measurements on…”
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Surface second harmonic generation from Si/SiO/sub 2/ and GaAs using 10-fs pulses by Cundiff, S.T., Knox, W.H., Baumann, F.H.

“…Summary form only given. The surface selectivity of surface second harmonic generation (SSHG) in centrosymmetric materials makes it a very powerful tool for…”
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Interface Properties of Strained InGaAs/InP Quantum Wells Grown by LP-MOVPE by Schwedler, R., Gallmann, B., Wolter, K., Kohl, A., Leo, K., Kurz, H., Juillaguet, S., Camassel, J., Laurenti, J. P., Baumann, F. H.

“…We have analysed ultrathin (5-10 monolayers) In 1-x Ga x As/InP (0.17 < x > 1) quantum wells grown by low-pressure metal organic vapour phase epitaxy using…”
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Junction delineation of 0.15 /spl mu/m MOS devices using scanning capacitance microscopy by Kleiman, R.N., O'Malley, M.L., Baumann, F.H., Garno, J.P., Timp, G.L.

“…With the increased scaling down of MOSFET dimensions, delineation of the p-n junction becomes increasingly important. We have studied cross-sectioned 0.15…”
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Direct channel length determination of sub-100 nm MOS devices using scanning capacitance microscopy by Kleiman, R.N., O'Malley, M.L., Baumann, F.H., Garno, J.P., Timp, W.G., Timp, G.L.

“…As MOSFET channel lengths are scaled to below 100 nm, the determination of the effective channel length, L/sub 0/ becomes increasingly important. We have…”
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50 nm Vertical Replacement-Gate (VRG) pMOSFETs by Sang-Hyun Oh, Hergenrother, J.M., Nigam, T., Monroe, D., Klemens, F.P., Kornblit, A., Mansfield, W.M., Baker, M.R., Barr, D.L., Baumann, F.H., Bolan, K.J., Boone, T., Ciampa, N.A., Cirelli, R.A., Eaglesham, D.J., Ferry, E.J., Fiory, A.T., Frackoviak, J., Garno, J.P., Gossmann, H.J., Grazul, J.L., Green, M.L., Hillenius, S.J., Johnson, R.W., Keller, R.C., King, C.A., Kleiman, R.N., Lee, J.T.-C., Miner, J.F., Morris, M.D., Rafferty, C.S., Rosamilia, J.M., Short, K., Sorsch, T.W., Timko, A.G., Weber, G.R., Wilk, G.D., Plummer, J.D.

“…We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor…”
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Dependence of gate oxide dielectric breakdown on S/D RTA by Kamgar, A., Vaidya, H.M., Baumann, F.H.

“…We have studied time dependent dielectric breakdown (TDDB) of very thin gate oxides, down to 1.5 nm, and have found unusual dependence on certain processing…”
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3D modeling of sputter and reflow processes for interconnect metals by Baumann, F.H., Gilmer, G.H.

“…We report full 3D Monte Carlo (MC) and molecular dynamics (MD) simulations of aluminum sputtering and reflow. The topography evolution and surface diffusion…”
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Impact of boron diffusion through O/sub 2/ and N/sub 2/O gate dielectrics on the process margin of dual-poly low power CMOS by Krisch, K.S., Manchanda, L., Baumann, F.H., Green, M.L., Brasen, D., Feldman, L.C., Ourmazd, A.

“…This work evaluates the impact of boron penetration from p/sup +/-polysilicon on process margin and system performance. We experimentally demonstrate that…”
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Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting, poly-Si intrusion, and corner stress by Liu, C.T., Baumann, F.H., Ghetti, A., Vuong, H.H., Chang, C.P., Cheung, K.P., Colonell, J.I., Lai, W.Y.C., Lloyd, E.J., Miner, J.F., Pai, C.S., Vaidya, H., Liu, R., Clemens, J.T.

“…In the fabrication of CMOS devices with sub-3 nm gate oxides, we have observed severe variation of the oxide thickness (t/sub ox/). For devices with 2.5 nm…”
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Precipitation of gold into metastable gold silicide in silicon by BAUMANN, F. H, SCHROÊTER, W

“…We report a detailed investigation of the precipitation behavior of gold in float-zone silicon from a highly supersaturated solution. Nucleation, morphology,…”
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