Search Results - "Basso, M.T."

65nm LP/GP mix low cost platform for multi-media wireless and consumer applications by Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Sabouret, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Biénacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouiller, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

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65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications by Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Sabouret, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Biénacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouiller, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

“…A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on…”
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65nm LP/GP mix low cost platform for multi-media wireless and consumer applications by Tavel, B., Duriez, B., Gwoziecki, R., Basso, M.T., Julien, C., Ortolland, C., Laplanche, Y., Fox, R., Saboure, E., Detcheverry, C., Boeuf, F., Morin, P., Barge, D., Bidaud, M., Bienacel, J., Garnier, P., Cooper, K., Chapon, J.D., Trouille, Y., Belledent, J., Broekaart, M., Gouraud, P., Denais, M., Huard, V., Rochereau, K., Difrenza, R., Planes, N., Marin, M., Boret, S., Gloria, D., Vanbergue, S., Abramowitz, P., Vishnubhotla, L., Reber, D., Stolk, P., Woo, M., Arnaud, F.

“…A complete 65nm CMOS platform, called LP/GP mix, has been developed employing thick oxide transistor (1.0), low power (LP) and general purpose (GP) devices on…”
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A conventional 45nm CMOS node low-cost platform for general purpose and low power applications by Boeuf, F., Arnaud, F., Basso, M.T., Sotta, D., Wacquant, F., Rosa, J., Bicais-Lepinay, N., Bernard, H., Bustos, J., Manakli, S., Gaillardin, M., Grant, J., Skotnicki, T., Tavel, B., Duriez, B., Bidaud, M., Gouraud, P., Chaton, C., Morin, P., Todeschini, J., Jurdit, M., Pain, L., De-Jonghe, V., El-Farhane, R., Jullian, S.

“…In this work, a low-cost 45nm node platform for general purpose and low power applications based on conventional bulk approach is proposed. Performant…”
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0.25 um NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity by Ada-Hanifi, M., Bonis, M., Verove, Ch, Basso, M.T., Revil, N., Haond, M., Lecontellec, M.

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Gate stack optimization for 65 nm CMOS low power and high performance platform by Duriez, B., Tavel, B., Boeuf, R., Basso, M.T., Laplanche, Y., Ortolland, C., Reber, D., Wacquant, R., Morin, P., Lenoble, D., Palla, R., Bidaud, M., Barge, D., Dachs, C., Brut, H., Roy, D., Marin, M., Payet, F., Cagnat, N., Difrenza, R., Rochereau, K., Denais, M., Stolk, P., Woo, M., Arnaud, F.

“…This paper demonstrates a full gate stack optimization by using post gate anneal (PGA) solution coupled with both germanium and fluorine gate predoping. We…”
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