Low-power logarithmic number system addition/subtraction and their impact on digital filters

This paper discusses techniques for low-power addition/ subtraction in the Logarithmic Number System (LNS) and evaluates their impact on digital filter implementation. Initially, the impact of partitioning the look-up tables (LUT) required for addition/subtraction on complexity, performance, and pow...

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Bibliographic Details
Published in:	2008 IEEE International Symposium on Circuits and Systems pp. 692 - 695
Main Authors:	Kouretas, I., Basetas, Ch, Paliouras, V.
Format:	Conference Proceeding Journal Article
Language:	English
Published:	IEEE 01-01-2008
Subjects:	Complexity theory Digital filters Floating-point arithmetic Power dissipation Signal processing Signal synthesis Software libraries Switching circuits Table lookup Very large scale integration
Online Access:	Get full text
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Summary:	This paper discusses techniques for low-power addition/ subtraction in the Logarithmic Number System (LNS) and evaluates their impact on digital filter implementation. Initially, the impact of partitioning the look-up tables (LUT) required for addition/subtraction on complexity, performance, and power dissipation is studied. Subsequently techniques for the low-power implementation of an LNS multiplyaccumulate (MAC) unit are investigated. The obtained LNS MACs are used for the design of digital filters. Synthesis of LNS-based digital filters using a 0.18μm 1.8V CMOS standard-cell library, reveal that significant power dissipation savings are possible at no performance penalty, when compared to linear two's-complement equivalent.
Bibliography:	ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23
ISBN:	9781424416837 1424416833
ISSN:	0271-4302 2158-1525
DOI:	10.1109/ISCAS.2008.4541512