Search Results - "Bartsch, Gunter"

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    A scalable model based RTL framework zamiaCAD for static analysis by Tsepurov, Anton, Bartsch, Gunter, Dorsch, Rainer, Jenihhin, Maksim, Raik, Jaan, Tihhomirov, Valentin

    “…As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous…”
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    Conference Proceeding Journal Article
  2. 2

    Localization of Bugs in Processor Designs Using zamiaCAD Framework by Tepurov, Anton, Tihhomirov, Valentin, Jenihhin, Maksim, Raik, Jaan, Bartsch, Gunter, Escobar, Jorge Hernan Meza, Wuttke, Heinz-Dietrich

    “…This paper proposes an approach to automatic localization of design errors (bugs) in processor designs based on combining statistical analysis of dynamically…”
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    Conference Proceeding
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    Automated Design Error Localization in RTL Designs by Jenihhin, Maksim, Tsepurov, Anton, Tihhomirov, Valentin, Raik, Jaan, Hantson, Hanno, Ubar, Raimund, Bartsch, Gunter, Escobar, JorgeHernan Meza, Wuttke, Heinz-Dietrich

    Published in IEEE design and test (01-02-2014)
    “…This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification…”
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    Magazine Article
  5. 5

    Some common aspects of design validation, debug and diagnosis by Arnaout, T., Bartsch, G., Wunderlich, H.J.

    “…Design, verification and test of integrated circuits with millions of gates put strong requirements on design time, test volume, test application time, test…”
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    Conference Proceeding
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