Search Results - "Bardsley, Scott"

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Bardsley, Scott, Dillon, Chris, McShea, Matthew, Periathambi, Joel Prabhakar, Puckett, Scott

“…We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold…”
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16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Bardsley, Scott, Dillon, Chris, Kumar, Mohit, McShea, Matthew, Bunch, Ryan, Prabhakar, Joel, Puckett, Scott

“…High sample rate ADCs with high input bandwidth and low power consumption enable direct RF sampling, more integration, flexibility and lower cost for…”
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A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration by Ali, A M A, Morgan, A, Dillon, C, Patterson, G, Puckett, S, Bhoraskar, P, Dinc, H, Hensley, M, Stop, R, Bardsley, S, Lattimore, D, Bray, J, Speir, C, Sneed, R

“…This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that…”
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A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter by Ali, A.M.A., Dillon, C., Sneed, R., Morgan, A.S., Bardsley, S., Kornblum, J., Lu Wu

“…This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35mum BiCMOS process. The ADC has a…”
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A 100-dB SFDR 80-MSPS 14-bit 0.35-μm BiCMOS pipeline ADC by BARDSLEY, Scott, DILLON, Christopher, KUMMARAGUNTLA, Ravi, LANE, Charles, ALI, Ahmed M. A, RIGSBEE, Baeton, COMBS, Darren

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A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration by Ali, A.M.A., Morgan, A., Dillon, C., Patterson, G., Puckett, S., Hensley, M., Stop, R., Bhoraskar, P., Bardsley, S., Lattimore, D., Bray, J., Speir, C., Sneed, R.

“…We present a 16b 250MS/S ADC that employs background calibration of the residue amplifier gain errors. It has an integrated input buffer and is fabricated on a…”
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A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither by Ali, Ahmed M. A., Dinc, Huseyin, Bhoraskar, Paritosh, Puckett, Scott, Morgan, Andy, Ning Zhu, Yu Qicheng, Dillon, Chris, Gray, Bryce, Lanford, Jon, McShea, Matt, Mehta, Ushma, Bardsley, Scott, Derounian, Peter, Bunch, Ryan, Moore, Ralph, Taylor, Gerry

“…We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling…”
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A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter by Ali, A.M.A., Dillon, C., Sneed, R., Morgan, A., Kornblum, J., Wu, L., Bardsley, S.

“…This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35 mum BiCMOS process. The ADC has an input…”
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A Tiered Security System for Mobile Devices by Bardsley, Scott, Thomas, Theodosios, Morris, R. Paul

“…We have designed a tiered security system for mobile devices where each security tier holds user-defined security triggers and actions. It has a friendly…”
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A frequency agile monolithic QPSK modulator with spectral filtering and 75 Ω differential line driver by Myers, B.A., Bardsley, S., Landy, P., Bell, T., Ross, R.

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