Search Results - "Baravelli, E.."

Impact of Line-Edge Roughness on FinFET Matching Performance by Baravelli, E.., Dixit, A.., Rooyackers, R.., Jurczak, M.., Speciale, N., De Meyer, K..

“…As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device…”
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Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance by Baravelli, E., Jurczak, M., Speciale, N., De Meyer, K., Dixit, A.

“…Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Among the sources of variability, line-edge-roughness (LER) and…”
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Theoretical analyses and modeling for nanoelectronics by Baccarani, G., Baravelli, E., Gnani, E., Gnudi, A., Reggiani, S.

“…In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the…”
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Wavelet Adaptivity for 3-D Device Simulation by De Marchi, L., Baravelli, E., Franze, F., Speciale, N.

“…A new technique has been implemented with the aim of providing an adaptive tool for the generation of computational meshes for 3-D semiconductor device…”
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Capacitance estimation for InAs Tunnel FETs by means of full-quantum k·p simulation by Gnani, E., Baravelli, E., Gnudi, A., Reggiani, S., Baccarani, G.

“…We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Nanowire Tunnel Field-Effect…”
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Wavelet-based adaptive mesh generation for device simulation by De Marchi, L., Franze, F., Baravelli, E., Speciale, N.

“…In this paper we propose a new method based on wavelet analysis, to define the discretization grid used to solve semiconductor devices PDE systems. We will…”
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Double-channel, frequency-steered acoustic transducer with 2-D imaging capabilities by Baravelli, E., Senesi, M., Ruzzene, M., De Marchi, Luca, Speciale, N.

“…A frequency-steerable acoustic transducer (FSAT) is employed for imaging of damage in plates through guided wave inspection. The FSAT is a shaped array with a…”
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Guided wave expansion in warped curvelet frames by De Marchi, Luca, Baravelli, E., Ruzzene, M., Speciale, N., Masetti, G.

“…Lamb wave testing for structural health monitoring (SHM) often relies on analysis of wavefields recorded through scanning laser Doppler vibrometers (SLDVs) or…”
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Theoretical analyses and modeling for nanoelectronics by Baccarani, G., Baravelli, E., Gnani, E., Gnudi, A., Reggiani, S.

“…In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the…”
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Optimization of staggered heterojunction p-TFETs for LSTP and LOP applications by Baravelli, E., Gnani, E., Grassi, R., Gundi, A., Baccarani, G.

“…Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al x Ga 1-x Sb TFETs is investigated, showing that cross-sections up to 10nm…”
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Complementary n- and p-type TFETs on the same InAs/Al0.05Ga0.95Sb platform by Baravelli, E., Gnani, E., Grassi, R., Gnudi, A., Reggiani, S., Baccarani, G.

“…Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al 0.05 Ga 0.95 Sb material pair is…”
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LER-induced limitations to VDD scalability of FinFET-based SRAMs with different design options by Baravelli, E., De Marchi, L., Speciale, N.

“…FinFET is a promising architecture for low-voltage/low-power applications at and beyond the 32 nm technology generation. V DD scalability of LSTP- and LOP-32…”
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Capacitance estimation for InAs Tunnel FETs by means of full-quantum k·p simulation by Baravelli, E., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.

“…We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Tunnel Field-Effect Transistor…”
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3D Mesh Generation with Wavelet-Driven Adaptivity by De Marchi, L., Baravelli, E., Franze, F., Speciale, N.

“…In this paper we show the effectiveness on 3-dimensional domains of a wavelet-based adaptive method (WAM), which is able to drive a progressive adaptation of…”
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Full-quantum simulation of heterojunction TFET inverters providing better performance than multi-gate CMOS at sub-0.35V VDD by Baravelli, E., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.

“…Tunnel FETs (TFETs) are promising alternatives to the conventional CMOS technology for steeper-than-60mV/dec subthreshold slopes (SS) required to limit power…”
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Photolithography-based realization of frequency steerable acoustic sensors on PVDF substrate by Baravelli, E., De Marchi, L., Ruzzene, M., Speciale, N.

“…Design, fabrication and testing of a frequency-steerable acoustic transducer (FSAT) is presented in this paper. The proposed device concept allows directional…”
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TCAD modeling and characterization of short-range variations in multiple-gate devices and circuit blocks by Baravelli, E., Speciale, N., Dixit, A., Jurczak, M.

“…Short-range process variations such as line-edge roughness (LER) and random dopant fluctuations (RD) are extremely critical in aggressively scaled devices. In…”
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Spectrogram remapping based imaging for spiral shaped frequency steerable acoustic transducers by Baravelli, E., De Marchi, L., Ruzzene, M., Speciale, N.

“…Guided Wave based Structural Health Monitoring greatly benefits from directional scanning. In contrast with conventional phased array approaches, the novel…”
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Warped-wigner-hough transformation of lamb waves for automatic defect detection by Perelli, A., De Marchi, L., Baravelli, E., Marzani, A., Speciale, N.

“…To improve the defect detectability of Lamb wave inspection systems, application of non-linear signal processing was investigated. The approach is based on a…”
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Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-Roughness by Dixit, A., Anil, K.G., Baravelli, E., Roussel, P., Mercha, A., Gustin, C., Bamal, M., Grossar, E., Rooyackers, R., Augendre, E., Jurczak, M., Biesemans, S., De Meyer, K.

“…Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time…”
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