Search Results - "Banerjee, Sudarshan"
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1
Trophic transfer patterns of arsenic in freshwater ecosystem layers in arsenic-endemic Ganges Delta and its potential human health risk
Published in Environmental science and pollution research international (01-12-2023)“…Arsenic (As) is a toxic environmental contaminant with global public health concern. In aquatic ecosystems, the quantification of total As is restricted…”
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Journal Article -
2
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration
Published in IEEE transactions on very large scale integration (VLSI) systems (01-11-2006)“…Partial dynamic reconfiguration is a key feature of modern reconfigurable architectures such as the Xilinx Virtex series of devices. However, this capability…”
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Journal Article -
3
Strip packing with precedence constraints and strip packing with release times
Published in Theoretical computer science (06-09-2009)“…The strip packing problem seeks to tightly pack a set of n rectangles into a strip of fixed width and arbitrary height. The rectangles model tasks and the…”
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Journal Article -
4
Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations
Published in IEEE transactions on very large scale integration (VLSI) systems (01-02-2009)“…Partial dynamic reconfiguration, often called run-time reconfiguration (RTR), is a key feature in modern reconfigurable platforms. In this paper, we present…”
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Journal Article -
5
Classification of Foods based on Ingredients
Published in 2023 International Conference on Computer Communication and Informatics (ICCCI) (23-01-2023)“…Due to the rise of recipe sharing websites, it is now quite easy to find online cooking instructions that list ingredients and cooking techniques. The…”
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Conference Proceeding -
6
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors
Published in IEEE transactions on very large scale integration (VLSI) systems (01-07-2006)“…Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded…”
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Journal Article Conference Proceeding -
7
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 42nd annual conference on Design automation; 13-17 June 2005 (13-06-2005)“…Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when…”
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Conference Proceeding -
8
Application mapping for platform FPGAs with partial dynamic reconfiguration
Published 01-01-2007“…Partial dynamic reconfiguration, frequently referred to as RTR, (Run-Time Reconfiguration), is a key feature available in the current generation of SRAM-based…”
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Dissertation -
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Application mapping for platform FPGAs with partial dynamic reconfiguration
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Dissertation -
10
Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures
Published in Annual ACM IEEE Design Automation Conference: Proceedings of the 44th annual conference on Design automation : San Diego, California; 04-08 June 2007 (04-06-2007)“…Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources…”
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Conference Proceeding -
11
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Published in Design, Automation and Test in Europe (07-03-2005)“…Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded…”
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Conference Proceeding -
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Performance and energy benefits of instruction set extensions in an FPGA soft core
Published in 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06) (2006)“…Performance of applications can be boosted by executing application-specific instruction set extensions (ISEs) on a specialized hardware coupled with a…”
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Conference Proceeding -
13
Energy-aware co-processor selection for embedded processors on FPGAs
Published in 2007 25th International Conference on Computer Design (01-10-2007)“…In this paper, we present co-processor selection problem for minimum energy consumption in hw/sw co-design on FPGAs with dual power mode. We provide…”
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Conference Proceeding -
14
Parallel Algorithm for Finding the Most Vital Edge in Weighted Graphs
Published in Journal of parallel and distributed computing (10-10-1997)“…LetG= (V,E) be a weighted undirected graph withnvertices andmedges; each edgeehas a weightw(e) assigned to it. Letf(G) be the weight of a minimum spanning tree…”
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Journal Article -
15
Efficient Search Space Exploration for HW-SW Partitioning
Published in Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004 (08-09-2004)“…Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for…”
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Conference Proceeding -
16
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures
Published in Proceedings of the 2006 Asia and South Pacific Design Automation Conference (24-01-2006)“…Partial dynamic reconfiguration, often called RTR (run-time reconfiguration) is a key feature in modern reconfigurable platforms. While partial RTR enables…”
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Conference Proceeding -
17
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Published 25-10-2007“…Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005) Customization of processor architectures through Instruction Set Extensions…”
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Journal Article -
18
Design space exploration of real-time multi-media MPSoCs with heterogeneous scheduling policies
Published in International Conference on Hardware Software Codesign: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis; 22-25 Oct. 2006 (22-10-2006)“…Real-time multi-media applications are increasingly being mapped onto MPSoC (multi-processor system-on-chip) platforms containing hardware-software IPs…”
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Conference Proceeding -
19
Efficient search space exploration for HW-SW partitioning
Published in International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004 (08-09-2004)“…Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for…”
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Conference Proceeding -
20
PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures
Published in Asia and South Pacific Conference on Design Automation, 2006 (2006)“…Partial dynamic reconfiguration, often called RTR (run-time reconfiguration) is a key feature in modern reconfigurable platforms. While partial RTR enables…”
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Conference Proceeding