Search Results - "Banerjee, Sudarshan"

Refine Results
  1. 1
  2. 2

    Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration by Banerjee, S., Bozorgzadeh, E., Dutt, N.D.

    “…Partial dynamic reconfiguration is a key feature of modern reconfigurable architectures such as the Xilinx Virtex series of devices. However, this capability…”
    Get full text
    Journal Article
  3. 3

    Strip packing with precedence constraints and strip packing with release times by Augustine, John, Banerjee, Sudarshan, Irani, Sandy

    Published in Theoretical computer science (06-09-2009)
    “…The strip packing problem seeks to tightly pack a set of n rectangles into a strip of fixed width and arbitrary height. The rectangles model tasks and the…”
    Get full text
    Journal Article
  4. 4

    Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations by Banerjee, S., Bozorgzadeh, E., Dutt, N.

    “…Partial dynamic reconfiguration, often called run-time reconfiguration (RTR), is a key feature in modern reconfigurable platforms. In this paper, we present…”
    Get full text
    Journal Article
  5. 5

    Classification of Foods based on Ingredients by Guria, Sudipa, Banerjee, Sudarshan, Bhattacharjee, Suddhasattwa, Paul, Swarup, Halder, Sobhan, Das, Priyanka

    “…Due to the rise of recipe sharing websites, it is now quite easy to find online cooking instructions that list ingredients and cooking techniques. The…”
    Get full text
    Conference Proceeding
  6. 6

    ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors by Biswas, P., Banerjee, S., Dutt, N.D., Pozzi, L., Ienne, P.

    “…Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded…”
    Get full text
    Journal Article Conference Proceeding
  7. 7

    Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration by Banerjee, Sudarshan, Bozorgzadeh, Elaheh, Dutt, Nikil

    “…Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when…”
    Get full text
    Conference Proceeding
  8. 8

    Application mapping for platform FPGAs with partial dynamic reconfiguration by Banerjee, Sudarshan

    Published 01-01-2007
    “…Partial dynamic reconfiguration, frequently referred to as RTR, (Run-Time Reconfiguration), is a key feature available in the current generation of SRAM-based…”
    Get full text
    Dissertation
  9. 9

    Application mapping for platform FPGAs with partial dynamic reconfiguration by Banerjee, Sudarshan

    “…Partial dynamic reconfiguration, frequently referred to as RTR, (Run-Time Reconfiguration), is a key feature available in the current generation of SRAM-based…”
    Get full text
    Dissertation
  10. 10

    Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures by Banerjee, Sudarshan, Bozorgzadeh, Elaheh, Dutt, Nikil, Noguera, Juanjo

    “…Partial dynamic reconfiguration (often referred to as partial RTR) enables true on-demand computing. A dynamically invoked application is assigned resources…”
    Get full text
    Conference Proceeding
  11. 11

    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement by Biswas, Partha, Banerjee, Sudarshan, Dutt, Nikil, Pozzi, Laura, Ienne, Paolo

    Published in Design, Automation and Test in Europe (07-03-2005)
    “…Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded…”
    Get full text
    Conference Proceeding
  12. 12

    Performance and energy benefits of instruction set extensions in an FPGA soft core by Biswas, P., Banerjee, S., Dutt, N., Ienne, P., Pozzi, L.

    “…Performance of applications can be boosted by executing application-specific instruction set extensions (ISEs) on a specialized hardware coupled with a…”
    Get full text
    Conference Proceeding
  13. 13

    Energy-aware co-processor selection for embedded processors on FPGAs by Gholamipour, A.H., Bozorgzadeh, E., Banerjee, S.

    “…In this paper, we present co-processor selection problem for minimum energy consumption in hw/sw co-design on FPGAs with dual power mode. We provide…”
    Get full text
    Conference Proceeding
  14. 14

    Parallel Algorithm for Finding the Most Vital Edge in Weighted Graphs by Banerjee, Sudarshan, Saxena, Sanjeev

    “…LetG= (V,E) be a weighted undirected graph withnvertices andmedges; each edgeehas a weightw(e) assigned to it. Letf(G) be the weight of a minimum spanning tree…”
    Get full text
    Journal Article
  15. 15

    Efficient Search Space Exploration for HW-SW Partitioning by Banerjee, Sudarshan, Dutt, Nikil

    “…Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for…”
    Get full text
    Conference Proceeding
  16. 16

    PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures by Banerjee, Sudarshan, Bozorgzadeh, Elaheh, Dutt, Nikil

    “…Partial dynamic reconfiguration, often called RTR (run-time reconfiguration) is a key feature in modern reconfigurable platforms. While partial RTR enables…”
    Get full text
    Conference Proceeding
  17. 17

    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement by Biswas, Partha, Banerjee, Sudarshan, Dutt, Nikil, Pozzi, Laura, Ienne, Paolo

    Published 25-10-2007
    “…Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005) Customization of processor architectures through Instruction Set Extensions…”
    Get full text
    Journal Article
  18. 18
  19. 19

    Efficient search space exploration for HW-SW partitioning by Banerjee, Sudarshan, Dutt, Nikil

    “…Hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for…”
    Get full text
    Conference Proceeding
  20. 20

    PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures by Banerjee, S., Bozorgzadeh, E., Dutt, N.

    “…Partial dynamic reconfiguration, often called RTR (run-time reconfiguration) is a key feature in modern reconfigurable platforms. While partial RTR enables…”
    Get full text
    Conference Proceeding